• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.9
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• pp.380-386
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• 2020

The ESS load test device (ELTD) can store and exchange electrical energy during the load test of an emergency generator. On the other hand, it is difficult to commercialize ELTDs based on Li-ion batteries because of the high initial cost, which is higher than a load bank test. If the trade of electrical energy stored in ELTD during the test of an emergency generator is considered, it may be possible to commercialize the ELTD. Therefore, this paper proposes an economic model of ELTD composed of the costs and benefits by considering electrical energy trade to perform accurately economic evaluations of an ELTD. From the simulation results of the economic evaluations of an ELTD and the load bank method, it was found that the commercialization of ELTD is possible when the trade in electrical energy in ELTDs is considered.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1517-1519
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• 1994

This paper describes electrical environmental study of a 765kV double circuit test line. Corona performance on several candidate conductor bundles has been investigated in the corona cage (single phase simulation facility) since 1984. We have known that six RAIL conductor bundle is the most suitable for the 765kV transmission Line, [3] To investigate electrical environmental impact of the future commerciale line, we build a full sacle 765kV test line in 1993. The test results of Audible Noise, Radio Interference, TV Interference from August, 1993 to Jan. 1994 were measured as $48.7[dBA](L_{50})$. $57.4[dB{\mu}V/m]$(Fair weather, $L_{50})$. $14.5[dB${\mu}$V/m]$(Fair weather, $L_{50}$). We have found that the Audible Noise data were very close to the predicted(48.5 [dBA]) by BPA Corona and Field Effects Computer program, however, the RI and TVI data were much higher than predicted(42 [dBmV/m], $7.9[dB{\mu}V/m)$ by the BPA program. We have investigating the reason of the difference. In the constructing of full scale test line, we developed the tubular tower, 765kV test transformer and hardwares of 765kV transmission line insulator strings. Also we will investigate the effects of plants under the 765kV test Line.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2046-2048
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• 2005

This paper deals with ground potential rise of structure grounding electrode when a test current flows through grounding electrode. In order to analyze the potential gradient of ground surface on structure grounding electrode, the reduced scale model has been used. The structures were designed through reducing real buildings and fabricated with four types on a scale of one-one hundred sixty. The supporter was made to put up with weight of structure and could move into vertical, horizontal, rotary direction. When a test current flowed through structure grounding electrodes, ground potential rise was the lowest value at electric cage type(type B). According to resistivity and absorption percentage in concrete attached to structure, the potential distribution of ground surface appeared differently.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.1
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• pp.85-92
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• 2011

The role of RCDs(Residual Current Protective Device) that are installed before the load is very important for preventing electric shock and electrical fire. However, although fault rate of RCD is increasing due to deterioration and long period usage, the RCD is permanently used without a checking of performance evaluation and it causes the electrical accident. In this paper, the amount of airborne chloride is researched in domestic costal area and the accelerated life test is conducted using a salt water spray tester in order to decide the life time of RCD. Aa a result of an accelerated life test, the MTTF(Mean Time To Failure) of RCD is 110.81 hours and B10 life time of RCD is 45.81 hours for the all samples. when an accelerated life test result is applied to within 2 km costal area, the life time of RCD is predicted about 5 years.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.3
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• pp.91-96
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• 2014

Modern electronic circuits are becoming more vulnerable to damage by surges, and it is required to improve the impulse withstand voltage performance of electrical and electronic equipment. This paper presents the impulse withstand voltage performance of lighting equipment connected to power lines, and the impulse withstand voltage tests for fluorescent lamp, LED lamp and halogen lamp were carried out according to the reference standards under normal service conditions. To conduct performance tests against lightning surge, a combination wave ($1.2/50{\mu}s$ voltage - $8/20{\mu}s$ current) was employed. The test surge was applied between lines or between line and ground of the specimen to be measured. The test surge was applied synchronized at the peak value of the positive and negative AC voltage waves. As a consequence, some specimens satisfied the impulse withstand voltage test criteria, but lighting equipment such as 36W fluorescent lamps, 5W and 5.5W LED lamps and 50W halogen lamp were damaged at the test voltage levels between power lines. It is needed to improve the qualities of lighting equipment to satisfy EMC immunity requirements of equipment for general lighting purposes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.147-155
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• 2017

A new endurance test-pattern generation on NAND-flash memory is proposed to improve test cost. We mainly focus on the correlation between the data-pattern and the device error-rate during endurance testing. The novelty is the development of testing method using quasi-random pattern based on device architectures in order to increase the test efficiency during time-consuming endurance testing. It has been proven by the experiments using the commercial 32 nm NAND flash-memory. Using the proposed method, the error-rate increases up to 18.6% compared to that of the conventional method which uses pseudo-random pattern. Endurance testing time using the proposed quasi-random pattern is faster than that of using the conventional pseudo-random pattern since it is possible to reach the target error rate quickly using the proposed one. Accordingly, the proposed method provides more low-cost testing solutions compared to the previous pseudo-random testing patterns.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.32-40
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• 2009

In order to reduce time-to-market, the demand for fast fault diagnosis has been increased. In this paper, a fault dropping technique with fault candidate ordering and test pattern ordering for fast fault diagnosis is proposed. Experimental results using the full-scanned ISCAS 89 benchmark circuits show the efficiency of the fault dropping technique with fault candidate ordering and test pattern ordering.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.740-754
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• 2015

This paper focuses on the reverse blocking busbar protection scheme with aim to improve the speed of its operation and at the same time to increase operational reliability, flexibility and stability of the protection during external and internal faults by implementation of the extended functionality provided by the IEC61850 standard-based protective Intelligent Electronic Devices (IEDs). The practical implementation of the scheme by the use of IEC 61850 standard communication protocol is investigated. The proposed scheme is designed for a radial type of a distribution network and is modeled and simulated in the DigSILENT software environment for various faults on the busbar and its outgoing feeders. A laboratory test bench is built using three ABB IEDs 670 series that are compliant with the IEC 61850 standard, CMC 356 Omicron test injection device, PC, MOXA switch, and a DC power supplier. Two types of the reverse blocking signals between the IEDs in the test bench are considered: hard wired and Ethernet communication by using IEC 61850 standard GOOSE messages. Comparative experimental study of the operational trip response speeds of the two implementations for various traffic conditions of the communication network shows that the performance of the protection scheme for the case of Ethernet IEC 61850 standard-based communication is better.

• Journal of Korean Physical Therapy Science
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• v.10 no.1
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• pp.65-73
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• 2003

The purpose of this study was to determine whether neuromuscular electrical stimulation(NMES), applied over the antagonist or the agonist, would alter the H reflex. Attention was focused on the roles of stimulus location. We used normal eight subjects without neuromuscular disease which were divided into 3 groups; the subjects were diveded into group of antagonist, agonist, antagonist-agonist. All groups were meted of eight subjects. Neuromuscular electrical stimulation was administered for 15 minutes. All subjects were subjected to three tests, including a pre-test, post-test and post-20 minute test. The data were analyzed by repeated measures ANOVA and paired t-test. The results were as follows; 1. H latencies were significantly increased in agonist and antagonist-agonist group (p<.01). 2. H/M intervals were significantly increased in agonist and antagonist-agonist group (p<.01). 3. H amplitudes were significantly increased in agonist (p<.001) and antagonist-agonist group (p<.01). 4. H/M ratios were significantly decreased in agonist and antagonist-agonist group (p<.01). In agonist group. H-reflex amplitudes and H/M ratios were more significantly decreased than antagonist group. Future studies will need to determine what influence NMES may have on the excitability of spinal motor neurons in people having UMN syndrome.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.478-483
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• 2014

We propose a new method which can extract the information about the electronic traps in the semi-insulating GaN buffer of AlGaN/GaN heterostructure field-effect transistors (HFETs) using a simple test structure. The proposed method has a merit in the easiness of fabricating the test structure. Moreover, the electric fields inside the test structure are very similar to those inside the actual transistor, so that we can extract the information of bulk traps which directly affect the current collapse behaviors of AlGaN/GaN HEFTs. By applying the proposed method to the GaN buffer structures with various unintentionally doped GaN channel thicknesses, we conclude that the incorporated carbon into the GaN back barrier layer is the dominant origin of the bulk trap which affects the current collapse behaviors of AlGaN/GaN HEFTs.