• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 2004.05a
• /
• pp.86-89
• /
• 2004

Recently polymer arresters are being used widely but we don't have appropriate long term characteristics test methods. Therefore we need to develop special test facility to evaluate long term reliability of polymer arresters. It's polymeric housing can be degraded by environmental stress and the interface between housing and inner module can be affected by moisture absorption. This moisture absorption can cause leakage current and tracking in the interface. We developed multi stress accelerated ageing test facility to simulate field conditions including UV, temperature, humidity, voltage, salt fog and rain. In addition, we carried out field exposure test at the outdoor test yard and characteristics analysis of field operated specimens to evaluate accelerating factor of this accelerated aging test.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.53 no.6
• /
• pp.457-464
• /
• 2004

Hard Disk Drive (HDD) test system is an equipment for the final test of HDD product by iterative read/write/seek test. This paper proposes an expert system for the fault diagnosis of HDD test systems. The purposed expert system is composed with two cascade inference, fuzzy logic and conventional binary logic. The fuzzy logic determines the possibility of the system fault using the test history data, then, the binary logic inferences the fault location of the test system. The proposed expert system is tested in SAMSUNG HDD production line, KUMI, KOREA, and shows satisfactory results.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.4
• /
• pp.796-800
• /
• 2011

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.61 no.7
• /
• pp.1041-1048
• /
• 2012

We display important test information from radar, telemetry in real time for monitoring and control of guided missile flight test. Clearing test area is the most important thing for safety. Thus, we have to constantly monitor and control ships around the test area. Several maritime surveillance radars are deployed around the test area for that purpose. However, multiple points are displayed for the same target when using multiple surveillance radars and this confuses the test personnel during the mission. In this paper, we suggested a method to solve this problem by analyzing error factor of surveillance radar and comparing the correlation of each radar data.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.915-916
• /
• 2007

There are many equipments for the Short Circuit Test, for example Short Circuit Generator, Induction Motor, Sequence Timer, Exciter, CLR, Back Up Breaker, Making Switch and TRV etc. Especially Back up Breaker and Making Switch are very important equipments to test the short circuit test. A role of a Back up Breaker is to break high-voltage and high-current for short circuit test and a Making Switch should be operated always same speed/time and kept electrical-mechanical characteristics to make the voltage and current of short circuit test. This study introduces to the short circuit test also to kinds, principal movements and compare them of Back up Breaker and Making Switch.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.7
• /
• pp.631-635
• /
• 2007

Diagnostic, surge and ac breakdown tests are widely used to evaluate the insulation condition of stator winding in traction motor. Diagnostic test included ac current, tan delta and maximum partial discharge. The result of diagnostic test indicates that five kinds of stator windings are good condition. Surge test was peformed to confirm the healthy of turn insulation in stator windings. This test is very easy to detect the turn insulation failure between normal and defect stator windings. After completing the diagnostic test, ac breakdown test has conducted gradually increasing ac voltage, until the stator winding punctured. No. 5 stator windings failed near rated voltage of 18.9 kV The breakdown voltage of No. 1 stator windings was 13.0 kV The ac breakdown voltage of normal winding is about 1.45 times higher than that of defect windings. The failure was located in a line-end coil at the exit from the core slot.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.68 no.2
• /
• pp.364-369
• /
• 2019

Generally, since memory chips should be tested all, considering its volume, the reduction in test time for detecting faults plays an important role in reducing the overall production cost. The parallel testing of chips in one ATE is a competitive solution to solve it. In this paper, NOC is proposed as test interface architecture between DUTs and ATE. Because NOC can be extended freely, there is no limit on the number of DUTs tested at the same time. Thus, more memory can be tested with the same bandwidth of ATE. Furthermore, the proposed NOC-based parallel test method can increase the efficiency of channel usage by packet type data transmission.

• Proceedings of the KIEE Conference
• /
• 1995.07a
• /
• pp.21-23
• /
• 1995

This paper is dealing with development of H/W and S/W of Retro-Fit NC lathe controller. Especially, S/W program is handling the tool nose radius compensation. A test of S/W program execution in the developed H/W has been made and its result showed a reasonable application in real practice.

• ETRI Journal
• /
• v.28 no.4
• /
• pp.475-485
• /
• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.140-150
• /
• 2006

In this paper, we present a new hardware architecture for testing various cores embedded in SoC. The conventional solutions need much testing time since only one core is tested at single test period. To enhance this, S-TAM, a novel test architecture, and its controller which enable parallel testing of various cores are proposed. S-TAM supports bus sharing to broadcast testing and cores to be tested are selected by using it. In addition, S-TAM controller enables the effective SoC test by simultaneous controlling the various test cores which are based on the different test architectures like IEEE 1149.1 and IEEE 1500.