• Transactions on Electrical and Electronic Materials
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• v.16 no.5
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• pp.254-259
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• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• Journal of Semiconductor Engineering
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• v.3 no.2
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• pp.161-167
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• 2022

Electrical characteristics of LDMOS power device with LDD(Lightly Doped Drain) structure is studied with variation of the region of channel and LDD. The channel in LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of CMOS inverter. Two-dimensional TCAD MEDICI simulation is used to study hot-carrier effect, on-resistance Ron, breakdown voltage, and transient switching characteristic. The voltage-transfer characteristics and on-off switching properties are studied as a function of the channel length and doping levels. The digital logic levels of the output and input voltages are analyzed from the transfer curves and circuit operation. Study indicates that drain current significantly depends on the channel length rather than the LDD region, while the switching transient time is almost independent of the channel length. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.825-828
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• 1992

In this paper, a Hybrid method for an effective channel length($L_{eff}$) on lightly doped drain(LDD) MOSFET's is proposed. In order to investigate the difference of the gate bias and substrate bias defendence of the $L_{eff}$ among various LDD structures, the $L_{eff}$ of the LDD's are extensively examined using simulations and measurement. one group is proposed for conventional MOSFET and the other group Is proposed for LDD MOSFET. It is shown that the $V_{bs}$-dependence of the n-region is different from $V_{gs}$-dependence of it.

• Proceedings of the KIEE Conference
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• 2007.10c
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• pp.80-82
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• 2007

This paper presents the overhang effects of a novel axial flux permanent magnet (AFPM) machine, which consist of the segmented stator and fractioned slot windings, with one rotor and double stator. In addition, the overhang effect of permanent magnet of the motor has been analyzed quantitatively. The overhang is used to enhance the force density in permanent magnet machine. According to the variation of overhang length, the flux density distribution and torque are quantitatively compared. For these analysis, three dimensional finite element method (3D FEM) has been used in this paper. From the results, the proper overhang length of PM is selected to improve the performance of the AFPM machine.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.478-481
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• 2003

We studied a periodic boundary effect in liquid crystal (LC) devices with multi-domains consisting of homeotropic and hybrid alignments. In this configuration, the surface anchoring energy was determined using the LC director-distorted length near the domain boundary, in a linear approximation of the director profile based on the continuum theory. The distorted length was measured in the LC binary diffraction grating.

• Journal of IKEEE
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• v.11 no.4
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• pp.252-256
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• 2007

We demonstrate that the effect of the PCB ground length and the cover is important in the performance of 2.4 GHz patch antennas. The Center frequency in the return loss shifts as much as 0.5 GHz, when the length of the PCB ground increases from 30 to 85 mm. The position of 10-dB bandwidth accordingly shifts to lower frequency region. Finally, the resonance at 2.4 GHz becomes stronger when the top cover exists. The radiation pattern of the patch antenna is also strongly affected by the ground structure and the existence of the top cover. In both the return loss and the radiation pattern, 3-dimensional simulations are shown to be an efficient tool.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2416-2419
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• 2009

We performed frequency response measurements of four tuning fork crystal oscillators with different sizes and analyzed their measured electrical equivalent circuit parameters of R, L, $C_S$, and $C_P$ as functions of the linear dimensions, length, width, and thickness. We observed that R and L showed an decreasing behavior with increasing length while $C_S$, and $C_P$ showed an increasing behavior. Similar dependences of the electrical parameters on thickness were also observed. On the contrary, any noticeable dependence of these parameters on width has not been found.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.132-138
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• 1997

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1621-1623
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• 1997

The breakdown voltage of SOI RESURF (REduce SURface Field) diode using a SIPOS (Semi Insulating POlycrystalline Silicon) layer is verified in terms of n-drift layer length and surface oxide thickness by device simulator MEDICI, and compared with conventional SOI RESURF diode. Increasing the n-drift layer length, the breakdown voltage of SOI RESURF diode using the SIPOS layer have increased and saturated at $8{\mu}m$. And it has decreased with increasing the surface oxide thickness.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.263-268
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• 2003

The Electrical insulation design and testing of high temperature superconducting (HTS) coil for high temperature superconducting fault current limiter (HTSFCL) has been performed. Electrical insulating factors of HTS coil for HTSFCL are turn-to-turn, layer-to-layer. The electrical insulation of turn-to-turn depends on surface length, and the electrical insulation of layer-to-layer depends on surface length and breakdown strength of L$N_2$. Therefore, two basic characteristics of breakdown and flashover voltage were experimentally investigated to design electrical insulation for 6.6㎸ Class HTSFCL. We used Weibull distribution to set electric field strength for insulation design. And mini-model HTS coil for HTSFCL was designed by using Weibull distribution and was manufactured to investigate breakdown characteristics. The mini-model HTS coil had passed in AC and Impulse withstand test.