• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1240-1248
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• 2006

In this paper, we present a new method for user selection, sub-band allocation, and power allocation in order to maximize the system throughput under the constraint of transmit power in multiuser downlink orthogonal frequency division multiple access (OFDMA) systems with partial channel quality information (CQI). In previous schemes, each user in one cell transmits CQI of all sub-bands to the base station, which requires enormous feedback overhead. Therefore, we proposed an efficient power allocation and modulation and coding selection scheme in which each user transmits partial CQI and one additional information to reduce the amount of feedback. Simulation results show that we can greatly reduce the amount of feedback than full feedback system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.310-317
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• 1993

This paper presents a mechanism for improving performance of the IEEE 802.6 MAN(Metropolitan Area Network), a dual-bus structured high-speed communication network, by a more efficient use of bandwidth. The MAN protocol is able to handle various traffic and offers better transmission speed than the conventional LAN, but the unidirectional bus structure and propagation delay of request bits results in unfairness since higher nodes use more bandwidth. As the number of stations and the distances between them are increased, the problem becomes mere serious. As a solution, this paper presents a method that every station enables to identify the used slots, and that a specified class denoted 'erasure station' has with the functions of destination release, slot reuse. As a result, it is export to improve network bandwidth values of each station and the throughput and delay time was analytically analyzed, and it is shown that according to computer simulation results, this mechanism improves the network performance.

• Biotechnology and Bioprocess Engineering:BBE
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• v.11 no.3
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• pp.235-239
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• 2006

Due to recent advances in genome sequencing, there has been a dramatic increase in the quantity of genetic information, which has lead to an even greater demand for a faster, more parallel expression system. Therefore, interest in cell-free protein synthesis, as an alternative method for high-throughput gene expression, has been revived. In contrast to in vivo gene expression methods, cell-free protein synthesis provides a completely open system for direct access to the reaction conditions. We have developed an efficient cell-free protein synthesis system by optimizing the energy source and S30 extract. Under the optimized conditions, approximately $650{\mu}g/mL$ of protein was produced after 2h of incubation, with the developed system further modified for the efficient expression of PCR-amplified DNA. When the concentrations of DNA, magnesium, and amino acids were optimized for the production of PCR-based cell-free protein synthesis, the protein yield was comparable to that from the plasmid template.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.52-60
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• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.797-800
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• 2011

The objective of MPEG Media Transport (MMT), which is on going standard, is to develop efficient delivery of media over packet based networks in an adaptive, progressive, download/streaming fashion over various IP based networks, including terrestrial, satellite and cable broadcast networks. In this paper we introduce utilization of signal strength information based on Cross Layer Design(CLD) to efficient multimedia delivery over wireless network in which in practice the wireless conditions can vary significantly. Many recent studies have shown that a significant improvement in wireless video throughput can be achieved by utilizing signal strength information on CLD [1][2]. Despite of its usefulness, however, it was difficult to employ signal strength information in rate adaptation applications due to different representation of signal strength information for each underlying wireless network. To that end, we proposed syntax and semantics of signal strength information in such a way that the information can be interpreted in the unified way. The proposed signal strength information was proposed for the MMT standardization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.87-95
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• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• Journal of the Korea Society of Computer and Information
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• v.16 no.9
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• pp.115-122
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• 2011

In this paper, we propose an efficient dynamic workload balancing strategy which improves the performance of high-performance computing system. The key idea of this dynamic workload balancing strategy is to minimize execution time of each job and to maximize the system throughput by effectively using system resource such as CPU, memory. Also, this strategy dynamically allocates job by considering demanded memory size of executing job and workload status of each node. If an overload node occurs due to allocated job, the proposed scheme migrates job, executing in overload nodes, to another free nodes and reduces the waiting time and execution time of job by balancing workload of each node. Through simulation, we show that the proposed dynamic workload balancing strategy based on CPU, memory improves the performance of high-performance computing system compared to previous strategies.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.830-833
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• 2007

In this paper, we implemented a $17{\times}17b$ binary digital multiplier using radix-4 Booth;s algorithmand proposed an efficient testing methodology for the full-custom design. A two-stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. Several chips were fabricated using LG Semicon 0.6-um 3-Metal N-well CMOS technology. We did fault simulations efficiently using the proposed test method resulting in the reduction of the number of faulty nodes by 88%. The chip contains 9115 transistors and the core area occupies $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10A
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• pp.965-973
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• 2007

We analyzed that the loss of data in TCP protocol based wireless networks caused by overlapped responses in bi-directional nodes that were resulted in out of the data sequence. This loss can be prevented by using revised TCP rate control algorithm and the performance of throughput can also be improved. The rate control algorithm is applied when the congestion happens between nodes while traffic packets are retransmitting in TCP bandwidth. In addition to applying the rate control algorithm, we determine the number of system clients in bandwidth and the average of pausing time between transmitting serial files to produce a competitive level so that an efficient performance of rapid retransmitting for the loss of multi-packets. This paper discusses the improvement of congestion control in that the decrease of the loss, firstly, as ensuring an efficient connection rate and, secondly, as using sliding window flow control.