• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1637-1640
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• 2005

This paper presents a technique for electromagnetic field analysis on surge response due to Mid-span back-flashovers effects in lightning protection system of 500 kV EHV single circuit transmission tower by the neural networks method. These analyses are based on modeling lightning return stroke as well as on coupling the electromagnetic fields of the stroke channel to the line. The ground conductivity influences both the electric field as well as the coupling mechanism and hence the magnitude and wave shape of the induced voltage. The technique can be used to analyzed the corona voltage effect, the effective of stroke to the span tower, the surge impedance of transmission lines. The maximum voltage from flashovers effects in the lines. The model is compatible with general electromagnetic transients programs such as the ATP-EMTP. The simulation results show that this study analyses for time-domain with those produced by a cascade multi-section model, the surge impedance of a full-sized tower hit directly by a lightning stroke is discussed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 E
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• pp.1578-1582
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• 1998

The ground potential rise generated by the switching surge or lightning stroke may be dangerous to personnel and cause damage to electronic control parts. For a first step to the transient performance analysis. high frequency impedances of grounding grids have been calculated and discussed. Grounding grids include 7 square grids from $10m{\times}10m$ to $80m{\times}80m$. The high frequency current was injected into the center and a corner of the grounding grid. The calculation results indicate that the impedance of the grounding grid is significantly influenced by frequency and the point of injection of the current. and the effective radius of a large grounding grid may be represented in $15{\sim}20m$.

• 대한전자공학회논문지SD
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• 제48권7호
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• pp.76-81
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• 2011

본 논문에서는 비아 절단 구조를 제안하고 2층 구조의 DRAM 패키지 기판 설계에 적용하여 낮은 임피던스를 가지는 파워 분배망(Power Distribution Network)을 구현하였다. 제안한 신규 비아 구조는 비아의 일부가 절단된 형태이고 본딩 패드와 결합하여 넓은 배선 면적을 필요로 하지 않는 장점을 가진다. 또한 비아 절단 구조를 적용한 설계에서는 본딩 패드에서 VSSQ까지의 배선 경로를 효과적으로 단축시킴으로써 PDN 임피던스를 개선시킬 수 있다. DRAM 패키지 기판 상의 윈도우 영역 형성과 동시에 비아의 일부 영역이 제거되므로 비아 절단 구조 제작을 위한 추가적인 공정은 없다. 또한 비아 홀 내부를 솔더 레지스트로 채움으로써 버(Burr) 발생을 최소화하였으며, 이를 패키지 기판 단면 촬영을 통해 검증하였다. 비아 절단 구조의 적용 및 VDDQ/VSSQ 배치에 의한 PDN 임피던스 변화를 검증하기 위해서 3차원 전자장 시뮬레이션 및 네트워크 분석기 측정을 통해 기존 방식을 적용한 패키지 기판과 비교 검증을 진행하였다. 신규 DRAM 패키지 기판은 대부분의 주파수 범위에서 보다 우수한 PDN 임피던스를 가졌으며, 이는 제안한 비아 절단 구조와 파워/그라운드 설계 배치가 PDN 임피던스 감소에 효과적임을 증명한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 A
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• pp.366-368
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• 2000

When faults occur in transmission lines, the classification of faults is very important. If the fault is HIF(High Impedance Fault), it cannot be detected or removed by conventional overcurrent relays (OCRs), and results in fire hazards and causes damages in electrical equipment or personal threat. The fast discrimination of fault needs to effective protection and treatment and is important problem for power system protection. This paper proposes the fault detection and discrimination algorithm for LIFs(Low Impedance Faults) and HIFs(High Impedance Faults). This algorithm uses artificial neural networks and variation of 3-phase maximum currents per period while faults. A double lines-to-ground and line-to-line faults can be detected using Neural Network. Also, the other faults can be detected using the value of variation of maximum current. Test results show that the proposed algorithms discriminate LIFs and HIFs accurately within a half cycle.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.493-498
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• 2004

The EMI noise source in a switching mode power supply is dominated by a common mode noise. If we can understand the common mode noise occurring mechanism, it is resulted to find out the method to suppress the EMI noise source in the switching mode power supply. The common mode noise is occurring mostly due to circuit is unbalanced which is caused by the capacitive coupling to frame ground, which passes through a heatsink of the switching devices. This research paper presents a new effective balancing method of buck converter circuit by mean of grounding the parasitic and compensation capacitors in correct proportion which is called that the common mode impedance balance (CMIB). The CMIB can be achieved by source, transmission line and termination balanced, such balancing, the common mode current will be cancelled out in the frame ground. The greatly reduced common mode noise can be confirmed by the experimental results.

• 전자공학회논문지A
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• 제32A권9호
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• pp.1250-1256
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• 1995

In this paper, shielded suspended coplanar waveguide with multiple anisotropic substrates is analyzed by the point matching method in the quasi-TEM mode appoximation. The characteristic impedance and the effective dielectric constant are calculated by varying the width of center strip and gap between the center strip and the ground strip. And also the characteristic parameters are calculated as a function of ${\varepsilon}_{x}/{\varepsilon}_{y}$) and a permitivity of the support substrate. Approaching the ground strip to infinity, the values of the characteristic parameters are found to be in good agreement with the other results by variational method.

• Journal of electromagnetic engineering and science
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• 제2권2호
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• pp.68-74
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• 2002

In this paper, a pre-layout design approach for high-speed microprocessor is proposed. For multilayer PCB stark up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system. The system model includes VRM, decoupling capacitors, multiple power and ground planes for core voltage, vias, as well as microprocessor. Finally, the simulation results are verified by measurements data.

• 대한전자공학회논문지SD
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• 제39권3호
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• pp.49-60
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• 2002

본 논문에서는 DRAM 모듈의 전원 평면에 대한 효과적인 설계 방법을 제시하였고 그 방법은 다음과 같이 세 단계로 구성되어 있다. 1) PEEC 등가회로를 이용한 2D 전송선 구조로 전원평면의 모델링 및 해석. 2) 측정값 비교를 통한 해석 결과 검증. 3) 전원 평면의 물리적 파라미터를 이용한 설계 가이드 제시. 제시한 내용을 바탕으로 하여 DRAM 모듈에서 전원 및 접지평면 성능을 안정화를 이루기 위한 효과적인 De-coupling 커패시터의 용량과 개수를 결정하는 방법을 기술하였다 이 설계 방법론은 스트립 구조 및 do-coupling 커패시터를 갖는 DRAM 모듈에서 효과적으로 사용할 수 있다.

• 대한전자공학회논문지TC
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• 제43권12호
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• pp.75-82
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• 2006

본 논문에서는 개구를 갖는 접지면의 높은 특성 임피던스를 이용하여 주파수에 대한 민감도가 좋고 높은 품질 계수를 갖는 미앤더 라인 인덕터들을 설계하였다. 주파수에 대한 민감도는 자기 공진 주파수 (SRF) 대신에 해석 주파수 범위에 대한 유효 인덕턴스 변화량으로 새로 정의 되었다. 등가 집중 소자 회로는 고주파 인덕터의 특성을 설명하기 위해 전개되었다. 개구 접지면을 갖는 4 nH 미앤더 라인 인덕터는 0.45 nH/GHz의 좋은 민감도와 0.7 GHz에서 86의 Q 값을 갖는다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.320-330
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• 2012

In this paper, we investigate the power integrity of grid structures for power and ground distribution on printed circuit board (PCB). We propose the 2D transmission line method (TLM)-based model for efficient frequency-dependent impedance characterization and PCB-package-integrated circuit (IC) co-simulation. The model includes an equivalent circuit model of fringing capacitance and probing ports. The accuracy of the proposed grid model is verified with test structure measurements and 3D electromagnetic (EM) simulations. If the grid structures replace the plane structures in PCBs, they should provide effective shielding of the electromagnetic interference in mobile systems. An analytical model to predict the shielding effectiveness (SE) of the grid structures is proposed and verified with EM simulations.