• Proceedings of the KSME Conference
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• 2005.11a
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• pp.223.1-223.1
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• 2005

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.6
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• pp.388-395
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• 1986

Dispersion characteristics of shielded single, coupled and edge-offset microstrip structures are investigated by using hybrid mode analysis with Galerkin's method in the spectral domain. Two new basis functions for the longitudinal strip current are proposed and convergence rates of the solutions for the basis functions are compared. Current distribution of the coupled line is obtaind from that of the single line by using shift theorem of the Fourier transform. In addition, effects of off-centered inner strip conductor on dispersion are also discussed Numerical results include various structual parameters and are compared with other available data and good agreements are observed.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.30 no.2 s.245
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• pp.141-148
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• 2006

In this paper, a new offset algorithm for closed 2D lines with islands is introduced and the result is illustrated. The main point of the proposed algorithm is that every point is set to be an offset by using bisectors, and then invalid offset lines, which are not to be participated in offsets, are detected in advance and handled with an invalid offset edge handling algorithm. As a result, raw offset lines without local invalid loops are generated. The proposed offset method is proved to be robust and simple, moreover, has a near O(n) time complexity, where n denotes the number of input lines. In addition, the proposed algorithm has been implemented and tested with 2D lines of various shapes.

• Journal of Sensor Science and Technology
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• v.14 no.3
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• pp.191-197
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• 2005

When fabricating a vision chip, we should consider the noise problem, such as the fixed pattern noise(FPN) due to the process variation. In this paper, we propose an edge-detection circuit based on biological retina using the offset-free column readout circuit to reduce the FPN occurring in the photo-detector. The offset-free column readout circuit consists of one source follower, one capacitor and five transmission gates. As a result, it is simpler and smaller than a general correlated double sampling(CDS) circuit. A vision chip for edge detection has been designed and fabricated using $0.35\;{\mu}m$ 2-poly 4-metal CMOS technology, and its output characteristics have been investigated.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.3
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• pp.412-418
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• 1999

The scattering characteristics of a prime-focus offset-parabolic antenna are analyzed using UTD. First, ray tracing method is used to locate the shadow boundaries, and then UTD is utilized to evalute the far-zone scattered magnetic field pattern. The field components included in the UTD analysis are the reflected, edge diffracted and creeping waves. The effects of circular caps attached to both edges of a prime-focus offset-parabolic antenna are investigated by comparing the scattered magnetic field patterns with those of a knife edge parabolic reflector.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.354-356
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• 2013

ITU와 ISO/IEC가 공동으로 UHD급 영상 부호화를 위해 표준화를 진행하고 있는 HEVC 코덱은 H.264/AVC 대비 2배 이상의 압축 효율을 갖는 것을 목표로 정하고 있다. HEVC(High Efficiency Video Coding)는 In-Loop Filter 기술로 H.264/AVC에서 사용하고 있는 Deblocking Filter와 새롭게 추가 된 SAO(Sample Adaptive Offset)를 사용하고 있다. 본 논문에서는 HEVC의 In-Loop Filter 기술 중 하나인 SAO의 기술의 EO에서 Category를 조금 더 정확하게 판단하여 분류하는 방법을 제안을 한다.

• Journal of Sensor Science and Technology
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• v.11 no.5
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• pp.255-262
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• 2002

Human retina is able to detect the edge of an object effectively. We designed a CMOS vision chip by modeling cells of the retina as hardwares involved in edge detection. There are several fluctuation factors which affect characteristics of MOSFETs during CMOS fabrication process and this effect appears as output offset of the vision chip which is composed of pixel arrays and readout circuits. The vision chip detecting edge information from input image is used for input stage of other systems. Therefore, the output offset of a vision chip determine the efficiency of the entire performance of a system. In order to eliminate the offset at the output stage, we designed a vision chip by using CDS(Correlated Double Sampling) technique. Using standard CMOS process, it is possible to integrate with other circuits. Having reliable output characteristics, this chip can be used at the input stage for many applications, like targe tracking system, fingerprint recognition system, human-friendly robot system and etc.

• ETRI Journal
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• v.32 no.3
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• pp.380-389
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• 2010

This paper presents a new edge-protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-protection maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 ${\mu}m$ CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.

• Structural Engineering and Mechanics
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• v.26 no.1
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• pp.99-109
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• 2007

A cracked composite specimen, comprised of an epoxy and an aluminium plate, was fractured under a tensile load. In this paper, two crack configurations were investigated. The first was an artificial center crack positioned in the epoxy plate parallel to the material interface. The other was for two edge cracks in the epoxy plate, again, parallel to the interface. A tensile test was carried out by gradually increasing the applied load and it was verified that the cracks always moved suddenly in an outward direction from the interface. The d/a ratio was gradually reduced to zero, and it was confirmed that the maximum stress intensity factor value for the artificial center crack, $K_{{\theta}{\theta}}^{max}$, approached that of an artificial interface crack,$K_{{\theta}{\theta}}^{ifc\;max}$ (where: 2a is the crack length and d is the offset between the crack and interface). The same phenomenon was also verified for the edge cracks. Specifically, when the offset, d, was reduced to zero, the maximum stress intensity factor value, $K_{{\theta}{\theta}}^{max}$, approached that of an artificial interface edge crack.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.290-291
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• 2013

Ab initio DFT 계산을 통해서 $Si/SiO_2$ 계면의 Band offset을 계산 했다. Si과 $SiO_2$ 각각의 물질을 계산한 결과로 얻은 로컬 퍼텐셜을 기준으로 Valence band와 Conduction band의 band edge의 위치를 결정할 수 있다. 그리고 계면 계산으로 얻은 로컬포텐셜을 이용하여 두물질의 로컬 퍼텐셜의 상대적인 위치를 결정할 수 있고 이를 이용하여 Band offset을 결정 할 수 있었다.