• 한국컴퓨터정보학회논문지
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• 제23권1호
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• pp.25-32
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• 2018

In this paper, we propose an edge detection algorithm for auto focus of infrared camera. We designed and implemented the edge detection of infrared image by using a spatial filter on FPGA. The infrared camera should be designed to minimize the image processing time and usage of hardware resource because these days surveillance systems should have the fast response and be low size, weight and power. we applied the $3{\times}3$ mask filter which has an advantage of minimizing the usage of memory and the propagation delay to process filtering. When we applied Laplacian filter to extract contour data from an image, not only edge components but also noise components of the image were extracted by the filter. These noise components make it difficult to determine the focus state. Also a bad pixel of infrared detector causes a problem in detecting the edge components. So we propose an adaptive edge detection filter that is a method to extract only edge components except noise components of an image by analyzing a variance of pixel data in $3{\times}3$ memory area. And we can detect the bad pixel and replace it with neighboring normal pixel value when we store a pixel in $3{\times}3$ memory area for filtering calculation. The experimental result proves that the proposed method is effective to implement the edge detection for auto focus in infrared camera.

• Journal of Information Processing Systems
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• 제17권1호
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• pp.191-202
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• 2021

In an Internet of Things (IoT)-configured system, each device executes on-chip software. Recent IoT devices require fast execution time of complex services, such as analyzing a large amount of data, while maintaining low-power computation. As service complexity increases, the service requires high-performance computing and more space for embedded space. However, the low performance of IoT edge devices and their small memory size can hinder the complex and diverse operations of IoT services. In this paper, we propose a remote on-demand software code execution unit using the cloudification of on-chip code memory to accelerate the program execution of an IoT edge device with a low-performance processor. We propose a simulation approach to distribute remote code executed on the server side and on the edge side according to the program's computational and communicational needs. Our on-demand remote code execution unit simulation platform, which includes an instruction set simulator based on 16-bit ARM Thumb instruction set architecture, successfully emulates the architectural behavior of on-chip flash memory, enabling embedded devices to accelerate and execute software using remote execution code in the IoT environment.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.109-110
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• 2007

Plasma etching process에서 magnetic field 영향에 관한 연구이다. High level dry etch process를 위해서는 high density plasma(HDP)가 요구된다. HDP를 위해서 MERIE(Magnetical enhancement reactive ion etcher) type의 설비가 사용되며 process chamber side에 4개의 magnetic coil을 사용한다. 이런 magnetic factor가 특히 wafer edge부문에 plasma charging에 의한 damage를 유발시키고 이로 인해 device Vth(Threshold voltage)가 shift 되면서 제품의 program 동작 문제의 원인이 되는 것을 발견하였다. 이번 연구에서 magnetic field와 관련된 plasma charge damage를 확인하고 damage free한 공정조건을 확보하게 되었다.

• 전자공학회논문지D
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• 제35D권12호
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• pp.48-52
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• 1998

본 논문에서는 SOI 기판 위에 새롭게 제안된 측면 채널과 나노 점을 갖는 나노 구조의 기억소자를 제작하였다. Top-silicon의 측면이 채널영역이 되고 나노 점이 이 채널 영역의 위에 반응성 이온 식각(RIE)에 의해 형성되는 구조를 가지는 이 소자는 측면 채널(edge channel)의 너비가 SOI기판의 열산화에 의해 얇아진 top-silicon의 두께에 의해 결정되고, 나노 점의 크기는 반응성 이온 식각(RIE) 및 전자선 직접 묘화에 의해 결정된다. 제작된 나노 구조 소자의 I/sub d/-V/sub d/, I/sub d/-V/sub g/ 특성 및 -20V에서 +14V까지의 게이트 전압 영역에서 문턱전압의 변화 범위가 약 1V정도 되는 기억소자의 특성을 얻었다.

• 대한임베디드공학회논문지
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• 제14권2호
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• pp.103-111
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• 2019

The IoT-driven large-scaled systems consist of connected things with on-chip executable embedded software. These light-weighted embedded things have limited hardware space, especially small size of on-chip flash memory. In addition, on-chip embedded software in flash memory is not easy to update in runtime to equip with latest services in IoT-driven applications. It is becoming important to develop light-weighted IoT devices with various software in the limited on-chip flash memory. The remote instruction execution in cloud via IoT connectivity enables to provide high performance software execution with unlimited software instruction in cloud and low-power streaming of instruction execution in IoT edge devices. In this paper, we propose a Cloud-IoT asymmetric structure for providing high performance instruction execution in cloud, still low power code executable thing in light-weighted IoT edge environment using remote instruction execution. We propose a simulated approach to determine efficient partitioning of software runtime in cloud and IoT edge. We evaluated the instruction cloudification using remote instruction by determining the execution time by the proposed structure. The cloud-connected instruction set simulator is newly introduced to emulate the behavior of the processor. Experimental results of the cloud-IoT connected software execution using remote instruction showed the feasibility of cloudification of on-chip code flash memory. The simulation environment for cloud-connected code execution successfully emulates architectural operations of on-chip flash memory in cloud so that the various software services in IoT can be accelerated and performed in low-power by cloudification of remote instruction execution. The execution time of the program is reduced by 50% and the memory space is reduced by 24% when the cloud-connected code execution is used.

• ETRI Journal
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• 제32권3호
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• pp.380-389
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• 2010

This paper presents a new edge-protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-protection maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 ${\mu}m$ CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.

• 한국멀티미디어학회논문지
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• 제1권2호
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• pp.194-203
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• 1998

본 논문에서는 VQ의 문제점인 에지의 열화 문제와 방대한 계산량을 해결하기 위한 새로운 DCT-VQ 방법을 제안한다. 에지 열화를 방지하기 위해 공간 영역에서 VQ를 하지 않고 DCT 변환 영역에서 VQ를 수행한다. DCT는 상관도가 높은 영상 데이타를 비상관화시키고, 적은 수의 계수에 에너지를 집중시키는 특정이 있다. DCT 변환 영역에서,DC 계수는 8비트 균일 스칼라 양자화하고,AC 계수는 에지 성분을 고려하 기 위해 3개 영역으로 구분하여 각 영역을 벡터 양자화한다. VQ의 계산량과 메모리의 절감을 위해 3개 영역의 벡터는 작은 차원($1{\times}7$)으로 구성되며 같은 부호책을 사용한다. 따라서 제안한 방법은 DCT 변환 계수의 고주파 성분올 고려함으로써 에지 성분을 최대한 살렬 수 있고, VQ의 벡터 차원을 줄임에 의해 계산량과 메모리를 크게 감소시킬 수 있다.

• Smart Structures and Systems
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• 제32권3호
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• pp.179-193
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• 2023

This study explores an alternative to the existing centralized process for data anomaly detection in modern Internet of Things (IoT)-based structural health monitoring (SHM) systems. An edge intelligence framework is proposed for the early detection and classification of various data anomalies facilitating quality enhancement of acquired data before transmitting to a central system. State-of-the-art deep neural network pruning techniques are investigated and compared aiming to significantly reduce the network size so that it can run efficiently on resource-constrained edge devices such as wireless smart sensors. Further, depthwise separable convolution (DSC) is invoked, the integration of which with advanced structural pruning methods exhibited superior compression capability. Last but not least, quantization-aware training (QAT) is adopted for faster processing and lower memory and power consumption. The proposed edge intelligence framework will eventually lead to reduced network overload and latency. This will enable intelligent self-adaptation strategies to be employed to timely deal with a faulty sensor, minimizing the wasteful use of power, memory, and other resources in wireless smart sensors, increasing efficiency, and reducing maintenance costs for modern smart SHM systems. This study presents a theoretical foundation for the proposed framework, the validation of which through actual field trials is a scope for future work.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.339-342
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• 1988

Typical magnetic bubble propagation failure modes of ion implanted magnetic bubble computer memory devices were observed and their failure mechanisms were analize. The skidding failure mode is due to the pushing of a strong repulsive charged wall. If this pushing is stronger than the edge affinity of the bubble in the cusp, the bubble moves out of the cusp when it is supposed to stay there. The stripeout failure modes across the adjacent track or along the track can be explained by considering the relative strength of the charged wall and the edge affinity encountered by both ends of the stripe. The skipping of the first cusp of a track is believed to be due to the whipping motion of the charged wall. The bubble moves directly to the second cusp via the long charged wall pointing to the second cusp skipping the first cusp.

• Journal of information and communication convergence engineering
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• 제8권1호
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• pp.51-58
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• 2010

This paper proposes an edge adaptive color interpolation for an ultra-small HD-grade complementary metal-oxide semiconductor (CMOS) video sensor in camera phones that can process 720-p/30-fps videos. Recently, proposed methods with great image quality perceptually reconstruct the green component and then estimate the red/blue component using the reconstructed green and neighbor red and blue pixels. However, these methods require the bulky memory line buffers in order to temporally store the reconstructed green components. The edge adaptive color interpolation method uses seven or nine patterns to calculate the six edge directions. At the same time, the threshold values are adaptively adjusted by the sum of the color values of the selected pixels. This method selects the suitable one among the patterns using two flowcharts proposed in this paper, and then interpolates the missing color values. For verification, we calculated the peak-signal-to-noise-ratio (PSNR) in the test images, which were processed by the proposed algorithm, and compared the calculated PSNR of the existing methods. The proposed color interpolation is also fabricated with the 0.18-${\mu}m$ CMOS flash memory process.