• Title/Summary/Keyword: dynamic power consumption

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Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems Using Efficient Slack Time Analysis (효율적인 슬랙 분석 방법에 기반한 경성 실시간 시스템에서의 동적 전압 조절 방안)

  • 김운석;김지홍;민상렬
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.12
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    • pp.736-748
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    • 2003
  • Dynamic voltage scaling(DVS), which adjusts the clock speed and supply voltage dynamically, is an effective technique in reducing the energy consumption of embedded real-time systems. The energy efficiency of a DVS algorithm largely depends on the performance of the slack estimation method used in it. In this paper, we propose novel DVS algorithms for periodic hard real-time tasks based on an improved slack estimation algorithm. Unlike the existing techniques, the proposed method can be applied to most priority-driven scheduling policies. Especially, we apply the proposed slack estimation method to EDF and RM scheduling policies. The experimental results show that the DVS algorithms using the proposed slack estimation method reduce the energy consumption by 20∼40 % over the existing DVS algorithms.

Power-Aware Scheduling for Mixed Real-Time Tasks (주기성과 산발성 태스크가 혼합된 시스템을 위한 전력절감 스케줄링 기법)

  • Gong, Min-Sik;Jeong, Gun-Jae;Song, Ye-Jin;Jung, Myoung-Jo;Cho, Moon-Haeng;Lee, Cheol-Hoon
    • The Journal of the Korea Contents Association
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    • v.7 no.1
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    • pp.83-93
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    • 2007
  • In this paper, we address a power-aware scheduling algorithm for a mixed real-time system which consists of periodic and sporadic tasks, each of which is characterized by its minimum period, worst-case execution requirement and deadline. We propose a dynamic voltage scaling algorithm called DVSMT(DVS for mixed tasks), which dynamically scales down the supplying voltage(and thus the frequency) using on-line distribution of the borrowed resources when jobs complete while still meeting their deadlines. With this scheme, we could reduce more energy consumption. As the proposed algorithm can be easily incorporated with RTOS(Real-Time Operating System), it is applicable for handhold devices and sensor network nodes that use a limited battery power. Simulation results show that DVSMT saves up 60% more than the existing algorithms both in the periodic-task and mixed-task systems.

Hierarchical Power Management Architecture and Optimal Local Control Policy for Energy Efficient Networks

  • Wei, Yifei;Wang, Xiaojun;Fialho, Leonardo;Bruschi, Roberto;Ormond, Olga;Collier, Martin
    • Journal of Communications and Networks
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    • v.18 no.4
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    • pp.540-550
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    • 2016
  • Since energy efficiency has become a significant concern for network infrastructure, next-generation network devices are expected to have embedded advanced power management capabilities. However, how to effectively exploit the green capabilities is still a big challenge, especially given the high heterogeneity of devices and their internal architectures. In this paper, we introduce a hierarchical power management architecture (HPMA) which represents physical components whose power can be monitored and controlled at various levels of a device as entities. We use energy aware state (EAS) as the power management setting mode of each device entity. The power policy controller is capable of getting information on how many EASes of the entity are manageable inside a device, and setting a certain EAS configuration for the entity. We propose the optimal local control policy which aims to minimize the router power consumption while meeting the performance constraints. A first-order Markov chain is used to model the statistical features of the network traffic load. The dynamic EAS configuration problem is formulated as a Markov decision process and solved using a dynamic programming algorithm. In addition, we demonstrate a reference implementation of the HPMA and EAS concept in a NetFPGA frequency scaled router which has the ability of toggling among five operating frequency options and/or turning off unused Ethernet ports.

Evaluation on Total Energy Consumption of Low-Energy House with Structural Insulated Panels (구조단열패널 적용 저에너지주택의 총에너지사용량 평가)

  • Lee, Hyeon-Ju;Nah, Hwan-Seon;Jo, Hye-Jin;Choi, Sung-Mo
    • Journal of the Korean Society for Advanced Composite Structures
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    • v.4 no.2
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    • pp.15-24
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    • 2013
  • This project is mainly related to evaluation of total energy consumption of low energy house, the exterior envelope of which was wholly composed of structural insulated panels(SIP). The U-value of applied SIP was in the range of 0.189 to $0.269W/m^2{\cdot}K$ and the U-value of pair glass from 0.78 to $1.298W/m^2{\cdot}K$ was applied for window dependent to its function respectively. For comparison of total energy performance, the energy simulation for pilot house was performed to compare with the control house having insulation criteria of Korean building regulation in 2009. Based on simulation of dynamic energy performance, the pilot house saved 48.3% of annual energy consumption while the control house in 2009 consumed as 85.7GJ/y. In case of heating, the result showed that the energy saving ratio amounted to 76.7%. For $CO_2$ emission, the pilot house diminished approximately 35.4% from $6,208.4kgCO_2$ to $4,009.2kgCO_2$. In payback period to early investment, it was analyzed the pilot house took 7.8 years, when the low energy house built by other insulation method with same thermal perfusion took 11.5 years. From this result, it is considered that the SIP is more effective, economic to Green Home application.

Design and Implementation of Hybrid Hard Disk I/O System based on n-Block Prefetching for Low Power Consumption and High I/O Performance (저전력과 입출력 성능이 향상된 n-블록 선반입 기반의 하이브리드 하드디스크 입출력 시스템 설계 및 구현)

  • Yang, Jun-Sik;Go, Young-Wook;Lee, Chan-Gun;Kim, Deok-Hwan
    • Journal of KIISE:Computer Systems and Theory
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    • v.36 no.6
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    • pp.451-462
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    • 2009
  • Recently, there are many active studies to enhance low I/O performance of hard disk device. The studies on the hardware make good progress whereas those of the system software to enhance I/O performance may not support the hardware performance due to its poor progress. In this paper, we propose a new method of prefetching n-blocks into the flash memory. The proposed method consists of three steps: (1)analyzing the pattern of read requests in block units; (2)determining the number of blocks prefetched to flash memory; (3)replacing blocks according to block replacement policy. The proposed method can reduce the latency time of hard disk and optimize the power consumption of the computer system. Experimental results show that the proposed dynamic n-block method provides better average response time than that of the existing AMP(Adaptive multi stream prefetching) method by 9.05% and reduces the average power consumption than that of the existing AMP method by 11.11%.

Development of HILS System for Performance Evaluation of a Heavy Commercial Vehicle Hybrid Electric Power Steering System (대형 상용차량 하이브리드 전동식 조향 시스템 주행 성능평가를 위한 HILS 시스템 개발)

  • Yoo, Chunsik;Choi, Gyoojae
    • Transactions of the Korean Society of Automotive Engineers
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    • v.25 no.1
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    • pp.103-110
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    • 2017
  • Most commercial vehicles have adopted the hydraulic power steering system. To reduce fuel consumption and to improve steering controllability, a hybrid electric power steering system is being developed for commercial vehicles. In this study, the HILS (Hardware In the Loop Simulation) system equipped with a commercial vehicle hybrid electric power steering system was developed and the vehicle dynamic performance of a truck with the steering system was evaluated. The hybrid electric power steering system is composed of the EHPS motor pump, column mounted EPS system, and ball nut steering gear box for heavy commercial vehicles. The accuracy of vehicle models equipped with the HILS system was verified with comparisons between the simulation results and field test results. The road reaction forces of the steering system were generated from the vehicle model and verified using field test results. Step steering tests using the verified HILS system were carried out and the performance of a newly developed commercial vehicle hybrid electric power steering system was evaluated.

A Microcomputer-Based Engine Performance Test System(I) (마이크로 컴퓨터를 이용(利用)한 엔진성능(性能) 측정장치(測定裝置) (I))

  • Min, Y.B.;Kim, Y.H.;Lee, K.M.;Huh, S.D.
    • Journal of Biosystems Engineering
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    • v.11 no.1
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    • pp.24-30
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    • 1986
  • In order to collect the engine performance data accurately, rapidly and reliabily, the microcomputer-based engine performance test system was developed and tested. The system measures engine shaft torque and speed, fuel consumption, exhaust gas temperature, engine shaft power and fuel consumption ratio. The system consisted of 32 channels 8 bit A/D converter, time clock, dynamic strain amplifier and signal conditioning circuits to amplify and filter the electrical signal from transducers. Most of transducers were devised for low cost, easy setting and self-manufacturing. The system has been installed on a small kerosene engine (DAEDONG NA50B).

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Cost-Efficient Framework for Mobile Video Streaming using Multi-Path TCP

  • Lim, Yeon-sup
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.16 no.4
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    • pp.1249-1265
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    • 2022
  • Video streaming has become one of the most popular applications for mobile devices. The network bandwidth required for video streaming continues to exponentially increase as video quality increases and the user base grows. Multi-Path TCP (MPTCP), which allows devices to communicate simultaneously through multiple network interfaces, is one of the solutions for providing robust and reliable streaming of such high-definition video. However, mobile video streaming over MPTCP raises new concerns, e.g., power consumption and cellular data usage, since mobile device resources are constrained, and users prefer to minimize such costs. In this work, we propose a mobile video streaming framework over MPTCP (mDASH) to reduce the costs of energy and cellular data usage while preserving feasible streaming quality. Our evaluation results show that by utilizing knowledge about video behavior, mDASH can reduce energy consumption by up to around 20%, and cellular usage by 15% points, with minimal quality degradation.

Design and Implementation for Portable Low-Power Embedded System (저전력 휴대용 임베디드 시스템 설계 및 구현)

  • Lee, Jung-Hwan;Kim, Myung-Jung
    • Journal of KIISE:Computing Practices and Letters
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    • v.13 no.7
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    • pp.454-461
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    • 2007
  • Portable embedded systems have recently become smaller in size and offer a variety of junctions for users. These systems require high performance processors to handle the many functions and also a small battery to fit inside the system. However, due to its size, the battery life has become a major issue. It is important to have both efficient power design and management for each function, while optimizing processor voltage and clock frequency in order to extend the battery life of the system. In this paper, we calculated the efficiency of power in optimizing power rail. This system has two microprocessors. One is used to play music and movie files while the other is for DMB. In order to reduce power consumption, the DMB microprocessor is turned of while music or videos are played. Lastly, DVFS is applied to the processor in the system to reduce power consumption. Experimental results of the implemented system have resulted in reduced power consumption.

A Fully Digital Automatic Gain Control System with Wide Dynamic Range Power Detectors for DVB-S2 Application (넓은 동적 영역의 파워 검출기를 이용한 DVB-S2용 디지털 자동 이득 제어 시스템)

  • Pu, Young-Gun;Park, Joon-Sung;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.9
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    • pp.58-67
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    • 2009
  • This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.