• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1606-1616
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• 1989

In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.

• ETRI Journal
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• v.41 no.3
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• pp.383-395
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• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.179-182
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• 2000

Adiabatic dynamic CMOS logic circuits, which are called ADCL circuits, promise us to implement low power logic circuits. Since the power supply source for ADCL circuits had not been developed, we proposed a power supply circuit for them. It is shown experimentally that by using the power supply circuit ADCL circuits can work with lower power consumption than conventional static CMOS circuit. In this paper, the power supply circuit is improved so that the power consumption can be reduced. Also, it is shown by some experiments that by using the circuit, ADCL circuits can work with lower power consumption than before Improving.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.10
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• pp.582-590
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• 2000

A fast optimal path planning algorithm using the analog Cellular Nonlinear Circuits(CNC) is proposed. The analog circuits based optimal path planning is very useful since most of the optimal path planning problems require real time computation. There has already been a previous study to implement the dynamic programming with analog circuits. However, it could not be applied for the practically large size of problems since the algorithm employs the mechanism of reducing its input current/voltage by the amount of cost, which causes outputs of distant cells to become zero. In this study, a subgoal-based dynamic programming algorithm to compute the optimal path is proposed. In the algorithm, the optimal paths are computed regardless of the distance between the starting and the goal points. It finds subgoals starting from the starting point when the output of the starting cell is raised from its initial value. The subgoal is set as the next initial position to find the next subgoal until the final goal is reached. The global optimality of the proposed algorithm is discussed and two different kinds of simulations have been done for the proposed algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.728-732
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• 2014

Macro-model of magnetic tunnel junction (MTJ) for spin transfer torque magnetic random access memory (STT-MRAM) has been developed. The macro-model can describe the dynamic behavior such as the state change of MTJ as a function of the pulse width of driving current and voltage. The statistical behavior has been included in the model to represent the variation of the MTJ characteristic due to process variation. The macro-model has been developed in Verilog-A.

• Proceedings of the KIEE Conference
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• 1999.07b
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• pp.540-542
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• 1999

We develop jumping ring system with sensor and control system using dynamic neural networks. Jumping ring, sensor and control system are controlled by 586 PC using Turbo C program. Sensor system is composed of 20 optical sensors and encoder. The control circuits are consisted of thyristor, FET and phase controller. A/D converter and optical sensor acquire real time motion data of the jumping ring system. The information of acquired jumping ring Position is estimated by using dynamic neural networks. Estimated control signals are sent to control circuits and D/A converter to track desired position of the jumping ring system. Experiment results are given to verify that proposed dynamic controller is useful in real jumping ring system.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.8
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• pp.1552-1564
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• 2002

Meter-in, meter-out and bleed-off circuits are widely utilized in order to adjust the speed of a hydraulic actuator by using a flow control valve and in order to regulate the pressure of a hydraulic volume by using a simple on-off valve. In these circuits, a relief valve serves either to maintain constant system pressure or to protect the system from over-pressure loading. The relief valve of a bleed-off circuit is the second case frequently undergoing on-off action during operation. It makes the analysis of the pressure control characteristics of the circuit highly difficult. In this paper, steady-state flow rate, pressure, heat loss and efficiency of the three circuits are reexamined and basic experiments far obtaining the characteristics of a pump and relief valve are conducted. Finally, simple empirical first-order dynamic models of decreasing and increasing pressure were separately proposed and verified by comparison with experiment. As the result, the basis for the theoretical analysis of the pressure control characteristics of a bleed-off circuit using a simple on-off valve is established.

• Journal of Power Electronics
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• v.15 no.2
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• pp.346-355
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• 2015

On the basis of the conventional PID control algorithm, a modified adaptive PID (MA-PID) control algorithm is presented to improve the steady-state and dynamic performance of closed-loop systems. The proposed method has a straightforward structure without excessively increasing the complexity and cost. It can adaptively adjust the values of the control parameters ($K_p$, $K_i$ and $K_d$) by following a new control law. Simulation results show that the line transient response of the MA-PID is better than that of the adaptive digital PID because the differential coefficient $K_d$ is introduced to changes. In addition, experimental results based on a FPGA indicate that the MA-PID control algorithm reduces the recovery time by 62.5% in response to a 1V line transient, 50% in response to a 500mA load transient, and 23.6% in response to a steady-state deviation, when compared with the conventional PID control algorithm.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.5
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• pp.478-486
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• 2000

This paper proposes a design method that can minimize the power dissipation of CMOS digital circuits without affecting their optimal operation speeds. The proposed method is based on genetic algorithms(GAs) combined to the retiming technique, a circuit transformation technique of repositioning flip-flops. The proposed design method consists of two phases: the phase of retiming for optimizing clock periods and the phase of GA retiming for minimizing power dissipation. Experimental results using Synopsys Design Analyzer show that the proposed design method can reduce the critical path delay of example circuits by about 30-50% and improve the dynamic power performance of the circuits by about 1.4~18.4%.

• Journal of Korean Vacuum Science & Technology
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• v.3 no.1
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• pp.66-73
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• 1999

In this paper, the design of one-chip FED system integrated with driving circuits in reported on the basis of MOSFET controlled FEA (MCFEA). To integrate a MOSFET with a FEA efficiently, a new fabrication process is proposed. It is confirmed that the MOSFET with threshold voltage of about 2volts controls the FEA emission current up to 20 ${\mu}$A by applying driving voltage of 15 volts, which is enough current level to utilize the MCFEA as a pixel for FED. The drain breakdown voltage of the MOSFET is measured to be 70 volts, which is also high enough for 60 volt operation of FED. The circuits for row and column driver are designed stressing on saving area, reducing malfunction probability and consuming low power to maximize the merit of on-chip driving circuits. Dynamic logic concept and bootstrap capacitors are used to meet these requirements. By integrating the driving circuit with FEA, the number of external I/O lines can be less than 20, irrespectively of the number of pixels.