• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
• /
• pp.2031-2033
• /
• 2005

poly-Si TFT의 kink 전류를 억제하는 L-shaped dual-gate TFT 구조를 제안하고 이를 제작하였다. 제안된 소자는 채널의 그레인 방향을 일정하게 성장시키는 SLS나 CW laser 결정화 방법을 사용한다. L자 모양의 게이트 구조를 사용하여 서고 다른 전계효과 이동도를 갖는 두 개의 sub-TFT를 구현할 수 있으며, 이러한 sub-TFT간의 특성차이가 kink 전류를 억제시킨다. 직접 제작한 L-shaped dual-gate 구조의 소자가 poly-Si TFT의 kink 전류를 억제하고, 전류포화 영역에서 전류량을 고정시킴으로써 신뢰성이 향상됨을 확인하였다.

• 한국전기전자재료학회논문지
• /
• 제15권3호
• /
• pp.233-237
• /
• 2002

A giga-bit DRAM(dynamic random access memory) technology with W/WNx/poly-Si dual gate electrode is presented in 7his papers. We fabricated $0.16\mu\textrm{m}$ CMOS using this technology and succeeded in suppressing short-channel effects. The saturation current of nMOS and surface-channel pMOS(SC-pMOS) with a $0.16\mu\textrm{m}$ gate was observed 330 $\mu\A/\mu\textrm{m}$ and 100 $\mu\A/\mu\textrm{m}$ respectively. The lower salutation current of SC-pMOS is due to the p-doped poly gate depletion. SC-pMOS shows good DIBL(dram-induced harrier lowering) and sub-threshold characteristics, and there was no boron penetration.

• 한국전기전자재료학회논문지
• /
• 제21권4호
• /
• pp.296-299
• /
• 2008

The effects of radio frequency (RF) source power for decoupled plasma nitridation (DPN) process on the electrical properties and Fowler-Nordheim (FN) stress immunity of the oxynitride gate dielectrics for deep nano-technology devices has been investigated. With increase of RF source power, the threshold voltage (Vth) of a NMOS transistor(TR) decreased and that of a PMOS transistor increased, indicating that the increase of nitrogen incorporation in the oxynitride layer due to higher RF source power induced more positive fixed charges. The improved off-current characteristics and wafer uniformity of PMOS Vth were observed with higher RF source power. FN stress immunity, however, has been degenerated with increasing RF source power, which was attributed to the increased trap sites in the oxynitride layer. With the experimental results, we could optimize the DPN process minimizing the power consumption of a device and satisfying the gate oxide reliability.

• 전자공학회논문지
• /
• 제51권3호
• /
• pp.177-184
• /
• 2014

화학기상증착의 텅스텐 실리사이드 듀얼 폴리 게이트 구조에서 플로린이 게이트 산화막에 미치는 영향을 전기적 물리적 측정 방법을 사용하여 연구하였다. 플로린을 많이 함유한 텅스텐 실리사이드 NMOS 트랜지스터에서 채널길이가 감소함에 따라 게이트 산화막 두께는 감소하여 트랜지스터의 롤업(roll-off) 특성이 심화된다. 이는 게이트 재 산화막 열처리 공정에 의해 수직방향으로의 플로린 확산과 더불어 수평방향인 게이트 측면 산화막으로의 플로린 확산에 기인한다. 채널길이가 짧아질수록 플로린의 측면방향 확산거리가 작아져 수평방향 플로린 확산이 증가하고 그 결과 게이트 산화막의 두께는 감소하게 된다. 반면에 PMOS 트랜지스터에서는 P형 폴리를 만들기 위한 높은 농도의 붕소가 플로린의 게이트 산화막으로의 확산을 억제하여 채널길이에 따른 산화막 두께 변화 특성이 보이지 않는다.

• 한국전기전자재료학회논문지
• /
• 제11권10호
• /
• pp.918-923
• /
• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
• /
• pp.193-196
• /
• 2002

This paper presents the improvement of the boron penetration and the reverse short channel effect (RSCE) in the 130nm W/WNx/Poly-Si dual gate PMOSFET for a high performance embedded DRAM. In order to suppress the boron penetration, we studied a range in the process heat budget. It has shown that the process heat budget reduction results in suppression of the boron penetration. To suppress the RSCE, we experimented with the halo (large tilt implantation of the same type of impurities as those in the device well) implant condition near the source/drain. It has shown that the low angle of the halo implant results in the suppression of the RSCE. The experiment was supported from two-dimensional(2-D) simulation, TSUPREM4 and MEDICI.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제8권2호
• /
• pp.156-163
• /
• 2008

We proposed a new $p^+/n^+$ gate locally-separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of $n^+$ poly-Si gate ($L_s$), the material filling the trench, and the width and length of the trench at a given gate length ($L_g$). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent $I_{off}$ suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable $L_s/L_g$ and channel fin width ($W_{cfin}$) at given $L_gs$ of 30 nm, 40 nm, and 50 nm.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
• /
• pp.519-522
• /
• 2002

In this paper, we analyze the impact of plasma etching process induced device degradation on low temperature poly-Si TFTs. The results indicate the relationship between device degradation and PPID effect during plasma fabrication. The dual-gate structure, which is used to suppress leakage current, is also discussed in this research.

• 전기학회논문지
• /
• 제56권9호
• /
• pp.1614-1618
• /
• 2007

We have demonstrated the experimental results to obtain the immunity of FN (Fowler Nordheim) stress for S-RCAT (Spherical-Recess Cell Array Transistor) which has been employed to meet the requirements of data retention time and propagation delay time for sub-100-nm mobile DRAM (Dynamic Random Access Memory). Despite of the same S-RCAT structure, the immunity of FN stress of S-RCAT depends on the process condition of gate oxidation. The S-RCAT using DPN (decoupled plasma nitridation) process showed the different degradation of device properties after FN stress. This paper gives the mechanism of FN-stress degradation of S-RCAT and introduces the improved process to suppress the FN-stress degradation of mobile DRAM.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
• /
• pp.281.2-281.2
• /
• 2016

Two-dimensional van der Waals (2D vdWs) materials have been extensively studied for future electronics and materials sciences due to their unique properties. Among them, black phosphorous (BP) has shown infinite potential for various device applications because of its high mobility and direct narrow band gap (~0.3 eV). In this work, we demonstrate a few-nm thick BP-based nonvolatile memory devices with an well-known poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] ferroelectric polymer gate insulator. Our BP ferroelectric memory devices show the highest linear mobility value of $1159cm^2/Vs$ with a $10^3$ on/off current ratio in our knowledge. Moreover, we successfully fabricate the ferroelectric complementary metal-oxide-semiconductor (CMOS) memory inverter circuits, combined with an n-type $MoS_2$ nanosheet transistor. Our memory CMOS inverter circuits show clear memory properties with a high output voltage memory efficiency of 95%. We thus conclude that the results of our ferroelectric memory devices exhibit promising perspectives for the future of 2D nanoelectronics and material science. More and advanced details will be discussed in the meeting.