• Journal of Power Electronics
• /
• v.14 no.6
• /
• pp.1217-1223
• /
• 2014

A novel half load-cycle worked dual input single output (DISO) DC/AC inverter is presented. The basic circuit consists of a dual buck regulator, which works in continuous current mode. The working principle of DISO DC/AC inverter has been used. The control method applied for half load-cycle worked DISO DC/AC inverter has been studied. The control effects of the open-loop proportional control and closed-loop proportional-integral control are compared by using PSIM software. The parameters are adopted in the realistic simulation and experiment test. Moreover, the waveforms, such as voltage of modulation reference signal and output voltage, were given. The simulation and experiment results proved that the half load-cycle worked DISO DC/AC inverter could achieve good performance, gain a line frequency of 50 Hz, and verify the correctness of theoretical analysis.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.12 no.4
• /
• pp.1458-1470
• /
• 2018

In this letter, a new dual-port Multiple-Input Multiple-Output (MIMO) antenna is introduced which has two independent signal feeding ports in a single antenna element to achieve smaller antenna volumes for the 5G mobile applications. The dual-port structure is implemented by adding a cross coupled semi-loop (CCSL) antenna as the secondary radiator to the ground short of inverted-F antenna (IFA). It is found that the port to port isolation is not deteriorated when an IFA and CCSL is combined to form a dual-port structure. The isolation property of the proposed antenna is compared with a polarization diversity based dual-port antenna proposed in the literature [9]. The operating frequency range is 3.3-4.0 GHz which is suitable for places where $4{\times}4$ MIMO systems are supposed to be deployed such as in China, EU, Korea and Japan at the band ${\times}$ (3.3 - 3.8GHz. The measured 6-dB impedance bandwidths of the proposed antennas are larger than 700 MHz with isolation between the feeding ports higher than 18 dB [1-2]. The simulation and measurement results show that the proposed antenna concept is a very promising alternative for 5G mobile applications.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.9 no.6
• /
• pp.578-583
• /
• 2016

In this paper, we propose a multi-mode wireless power transfer (WPT) system with a dual loop structure. The proposed multi-mode WPT system consist of outer loop module which can operate at two different frequency bands including 6.78 MHz magnetic resonance WPT mode and 13.56 MHz near field communication (NFC) mode and inner loop module connected with outer loop which can operate at two different frequency bands including WPC mode and PMA mode based on inductive coupling standards. In order to be able to embed this system into smartphone battery back cover, the electrical designs are optimized and then the size was fixed $45{\times}90{\times}0.35mm3$ (including ferrite sheet) which is the same commercial smartphone. The proposed multi-mode WPT module can cover WPC and PMA mode based on inductive coupling. Moreover, it has more than 20 dB return loss characteristics at two different frequency bands including 6.78 MHz and 13.56 MHz, and shows more than 70 % transfer efficiency between resonant coils at 6.78 MHz in magnetic resonant charging environment.

• Journal of Power Electronics
• /
• v.12 no.6
• /
• pp.886-894
• /
• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.3 no.2 s.5
• /
• pp.69-74
• /
• 2004

In this work, A PLDRO (Phase Locked Dielectric Resonator Oscillator) which can be used for the wireless communication systems fur MMC(Microwave Micro Cell) and ITS wireless communication system is designed. A different approach to the PLDRO structure is applied for phase locking by dual phase lock loop structure. The proposed dual loop PLDRO generates the output power of 0 dBm at 18.7 GHz and has the characteristics of a phase noise of -80 dBc/Hz at 1kHz, -83 dBc/Hz at 10 kHz offset frequency from carrier frequency

• ETRI Journal
• /
• v.30 no.2
• /
• pp.268-274
• /
• 2008

This paper proposes an open-loop clock recovery circuit (CRC) using two high-Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual-mode operation. The DR filters are fabricated to obtain high Q-values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak-to-peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo-random binary sequence (PRBS) data with a word length of $2^{31}-1$ are less than 2.0 ps and 0.3 ps, respectively. The peak-to-peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error-free operation of the 40 Gb/s-class optical receiver with the dual-mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.6
• /
• pp.408-420
• /
• 2003

This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.12
• /
• pp.84-89
• /
• 2010

In this paper, a novel voltage-controlled oscillator (VCO) using the microstrip square open loop dual split ring resonator is presented for reducing the phase noise. The square-shaped dual split ring resonator having the form of the microstrip square open loop is investigated to reduce the phase noise. Compared with the microstrip square open loop resonator and the microstrip square open loop split ring resonator as well as the conventional microstrip line resonator, the microstrip square dual split ring resonator has the larger coupling coefficient value, which makes a higher Q value, and has reduced the phase noise of VCO. The VCO with 1.7V power supply has the phase noise of -123.2~-122.0 dBc/Hz @ 100 kHz in the tuning range, 11.74~11.75 GHz. The figure of merit (FOM) of this VCO is-214.8~-221.7 dBc/Hz dBc/Hz @ 100 kHz in the same tuning range. Compared with VCO using the conventional microstrip line resonator, VCO using microstrip square open loop resonator, the phase noise of VCO using the proposed resonator has been improved in 26 dB, 10 dB, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.23 no.5
• /
• pp.551-558
• /
• 2012

This paper presents a dual band loop-type ground antenna using lumped-elements that control the impedance bandwidth and resonant frequency. The dual-band operation of the proposed antenna is realized by inserting an additional resonated loop feed structure into the reference ground antenna. As the proper value of the capacitor and the inductor are chosen, the impedance bandwidth of our antenna with voltage standing wave ratio(VSWR) equal to 3 is 85 MHz and 725 MHz at the 2.45 and 5.5 GHz frequency band, respectively. Its validity is demonstrated via both the computed and measured results. Good antenna patterns and efficiencies are achieved at the dual frequency bands, as well as the physically small antenna element size($10{\times}5mm^2$).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.29 no.11
• /
• pp.898-905
• /
• 2018

In this work, infrared targets for a developed hardware-in-the-loop simulation(HILS) system are proposed for a performance test of a dual-sensor imaging seeker equipped with an infrared and a visible sensor that can lock and track for ground and air targets. This integrated system is composed of 100 modules of heat and light sources to simulate various kinds of target and the trajectory of moving targets based on scenarios. It is possible to simulate not only the position, velocity, and direction for these targets but also background clutter and jamming environments. The design and measurement results of an infrared target, such as the HILS system configuration, developed for testing and evaluation of a dual-sensor imaging seeker are described. In the future, it is planned to test the lock-on and tracking performance of an imaging seeker equipped with single or dual sensors dynamically in real time based on a simulation flight scenario in the developed HILS system.