• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.2
• /
• pp.152-156
• /
• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.7
• /
• pp.1552-1558
• /
• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 2000.11a
• /
• pp.237-242
• /
• 2000

The areal recording density of HDD(Hard Disk Drive) has been increasing by about 60% a year. In order to achieve high areal density, less track pitch is expected and more servo bandwidth is required. Dual stage actuator and servo controller for HDD have been suggested for achieving high track density as a possible solution. Dual-loop servo system is generally classified into a two-input-two-output system, but if we use an estimator for a two-input-two-output system, it can be converted into two input one output system. Since we can't control the dual stage servo system by the classical method, it requires a special technique; for example, Parallel Loop System, Master-Slave Loop System, Decoupled Master-Slave Loop System, and Dual Feedback Loop System. In this paper, we performed experimental evaluations of several types of control algorithm. Further experiments will be made in the future.

• Journal of Power Electronics
• /
• v.16 no.4
• /
• pp.1565-1577
• /
• 2016

For grid-connected LCL-filtered inverters, dual-loop current control with an inner-loop active damping (AD) based on capacitor current feedback is generally used for the sake of current quality. However, existing studies on capacitor current feedback AD with a control delay do not reveal the mathematical relation among the dual-loop stability, capacitor current feedback factor, delay time and LCL parameters. The robustness was not investigated through mathematical derivations. Thus, this paper aims to provide a systematic study of dual-loop current control in a digitally-controlled inverter. At first, the stable region of the inner-loop AD is derived. Then, the dual-loop stability and robustness are analyzed by mathematical derivations when the inner-loop AD is stable and unstable. Robust design principles for the inner-loop AD feedback factor and the outer-loop current controller are derived. Most importantly, ensuring the stability of the inner-loop AD is critical for achieving high robustness against a large grid impedance. Then, several improved approaches are proposed and synthesized. The limitations and benefits of all of the approaches are identified to help engineers apply capacitor current feedback AD in practice.

• Journal of electromagnetic engineering and science
• /
• v.17 no.3
• /
• pp.138-146
• /
• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.61 no.1
• /
• pp.5-9
• /
• 2012

In this paper, multi folded dual monopole antenna for WLAN communication of dual bend is designed and fabricated. The proposed multi folded dual monopole antenna are consisted of two folded rectangle loops by microstrip fed that is modified dual monopole antenna. Therefore, the outside rectangle loop structure of the proposed antenna is extended a dual monopole. The characteristics of the proposed antenna is analyzed return loss and radiation patterns by the FDTD tools. As a result a bandwidth of proposed antenna has about 0.82GHz from 2.0 to 2.82[GHz] and 0.7GHz from 5.46 to 6.16[GHz]. It is used WLAN communications of 2[GHz] and 5[GHz].

• Transactions of the Korean Society of Automotive Engineers
• /
• v.18 no.5
• /
• pp.136-144
• /
• 2010

Exhaust gas recirculation (EGR) is an emission control technology allowing significant NOx emission reduction from light-and heavy duty diesel engines. The future EGR type, dual loop EGR, combining features of high pressure loop EGR and low pressure loop EGR, was developed and optimized by using a commercial engine simulation program, GT-POWER. Some variables were selected to control dual loop EGR system such as VGT (Variable Geometry Turbocharger)performance, especially turbo speed, flap valve opening diameter at the exhaust tail pipe, and EGR valve opening diameter. Applying the dual loop EGR system in the light-duty diesel engine might cause some problems, such as decrease of engine performance and increase of brake specific fuel consumption (BSFC). So proper EGR rate (or mass flow) control would be needed because there are trade-offs of two types of the EGR (HPL and LPL) features. In this study, a diesel engine under dual loop EGR system was optimized by using design of experiment (DoE). Some dominant variables were determined which had effects on torque, BSFC, NOx, and EGR rate. As a result, optimization was performed to compensate the torque and BSFC by controlling start of injection (SOI), injection mass and EGR valves, etc.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.5
• /
• pp.82-87
• /
• 2008

This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a $0.35{\mu}m$ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was $2.2{\mu}s$ and that of the single-slope phase-locke loop was $7{\mu}s$.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.829-832
• /
• 2005

This paper describes a wide-range dual-loop Delay Locked Loop (DLL) using Voltage Controlled Delay Line (VCDL) based on Transmission Gate(TG) inverters. One loop is used when the minimum VCDL delay is greater than a half of $T_{REF}$, the reference clock period. The other loop is initiated when the minimum delay is less than $0.5{\times}T_{REF}$. The proposed VCDL improves the dynamic operation range of a DLL. The DLL with a VCDL of 10 TG inverters provides a lock range from 70MHz to 700MHz when designed using $0.18{\mu}m$ CMOS technology with 1.8 supply voltage. The DLL consumes 11.5mW for locking operation with a 700MHz reference clock. The proposed DLL can be used for high-speed memory devices and processors, communication systems, high-performance display interfaces, etc.

• Proceedings of the KIEE Conference
• /
• 1991.11a
• /
• pp.175-178
• /
• 1991

The drive system of servo motor is requested to have robustness of disturbance and parameter variation. However, the dynamics of PMSM drive change significantly by forced disturbance and parameter variation. Moreover, the state error caused by them should be suppressed completely and rapidly. In this paper, the vector-control system of PMSM using dual adaptive control loop is investigated. In the proposed system, linear adaptive control loop rapidly recovers the state error caused by both disturbance and parameter variation. In the dual adaptive control loop, the inner loop reduces the system sensitivity of parameter variation and disturbance, and the outer loop suppresses the state error caused by them completely. The proposed servo system is verified through a computer simulations and experimental results.