• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.3
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• pp.93-98
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• 2005

STSAT-2 will be launched on December 2007 by the first Korean launch vehicle KSLV-1, and its one of the main instruments is DREAM (Dual Channel Radio Frequency and Environment Atmosphere Monitoring) which detects a signal for atmosphere from the Earth by using micro-wave signal. The STSAT-2 has many units for technology demonstration such as FDSS (Fine Digital Sun Sensor) and DHST (Dual Head Star Tracker) including PPT (Pulsed Plasma Thruster) for attitude control and momentum dumping in the space. In this paper, the power budget analysis for STSAT-2 will be studied and provided for supporting the whole mission life time during the mission of its spacecraft.

• Atmosphere
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• v.29 no.2
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• pp.197-211
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• 2019

The observational sensitivity of dual-polarization weather radar was quantitatively analyzed by using two different pulse widths. For this purpose, test radar scan strategy which consisted of consecutive radar scan using long (LP: $2{\mu}s$) and short (SP: $1{\mu}s$) pulses at the same elevation angle was employed. The test scan strategy was conducted at three operational S-band dual-polarization radars (KSN, JNI, and GSN) of Korea Meteorological Administration (KMA). First, the minimum detectable reflectivity (MDR) was analyzed as a function of range using large data set of reflectivity ($Z_H$) obtained from JNI and GSN radars. The MDR of LP was as much as 7~22 dB smaller than that of SP. The LP could measure $Z_H$ greater than 0 dBZ within the maximum observational range of 240 km. Secondly, polarimetric observations and the spatial extent of radar echo between two pulses were compared. The cross-polar correlation coefficient (${\rho}_{hv}$) from LP was greater than that from SP at weak reflectivity (0~20 dBZ). The ratio of $Z_H$ (> 0 dBZ) and ${\rho}_{hv}$(> 0.95) bin to total bin calculated from LP were greater than those from SP (maximum 7.1% and 13.2%). Thirdly, the frequency of $Z_H$ (FOR) during three precipitation events was analyzed. The FOR of LP was greater than that of SP, and the difference in FOR between them increased with increasing range. We conclude that the use of LP can enhance the sensitivity of polarimetric observations and is more suitable for detecting weak echoes.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.877-880
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• 2005

This paper describes a PLL frequency synthesizer for wireless LNA applications. The design is focused mainly on low-power and low-phase noise characteristics. A 128/129 dual-modulus prescaler has been designed using the proposed TSPC D flip-flops for high-speed operation and low-power consumption The designed synthesizer includes all building blocks for elimination of external components, other than the crystal. Its operating frequency can be programmed by external data. The frequency synthesizer has been designed using a $0.25{\mu}m$ CMOS process parameters. It operates in the frequency range of 2GHz to 3GHz and consumes 3.2mA at 2.5GHz from a 2.5V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.6
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• pp.736-743
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• 2020

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.5
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• pp.419-426
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• 2002

A new active lossless snubber for half-bridge dual converter(that is called'dual converter') is proposed in this paper It features soft switching(ZVS) as well as turn-off snubbing in both main and auxiliary switches. Therefore, it helps the dual converter to operate at the higher frequency with a higher efficiency and smaller-sized reactive components. Moreover, since it uses parasitic components, such as leakage inductances and switch output capacitances etc, to achieve the ZVS of power switches, it has simpler structure and lower cost of production. The operational principle, theoretical analysis, and design consideration are presented. To confirm the operation, features, and validity of the proposed circuit, experimental results from a 200w, 24V/DC-200V/DC proto-type are presented.

• ETRI Journal
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• v.39 no.5
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• pp.756-763
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• 2017

A switchable single-wideband (SWB)-to-dual-wideband (DWB) bandpass filter (BPF), which is realized by using lumped switches, is presented in this paper. By alternating the operation modes-ON and OFF-in which the ON mode is achieved by placing the capacitors at the switching spots and the OFF mode is achieved by replacing the capacitors with inductors, DWB-to-SWB BPF can be achieved on the same device. In addition, by changing the capacitor values, the center frequency (CF) of the lower passband of DWB BPF can be easily tuned from 1.69 GHz to 2.22 GHz, while the higher passband stays almost unchanged. As an example, an SWB-to-DWB BPF is designed, fabricated, and measured. This BPF exhibits good performance including wideband, high isolation, compact size, and ability to switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.619-624
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• 2002

In this paper, a novel architecture of programmable divider with fifty percent duty cycle output and programmable dividing number has been proposed. Through HSPICE simulation, a 900MHz frequency synthesizer with proposed (sequency divider has designed in a standard 0.25㎛ CMOS technology To verify the operation of proposed frequency divider, a chip had been fabricated using 0.65㎛ 2-poly, 3-metal standard CMOS processing and experimental result shows that the proposed frequency divider works well. The designed voltage controlled oscillator(VCO) has a center frequency of 900MHz a tuning range of $\pm$10%, and a gain of 154HHz/V. The simulated frequency synthesizer performance has a settling time of 1.5$\mu$s, a frequency range from 820MHz to IGHz and power consumption of 70mW at 2.5V power supply voltage.

• Journal of Power Electronics
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• v.10 no.2
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• pp.155-164
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• 2010

This paper presents a voltage control algorithm for a hybrid multilevel inverter based on a staged-perception of the inverter voltage vector diagram. The algorithm is applied to control a three-stage eighteen-level hybrid inverter, which has been designed with a maximum number of symmetrical levels. The inverter has a two-level main stage built using a conventional six-switch inverter and medium- and low- voltage three-level stages constructed using cascaded H-bridge cells. The distinctive feature of the proposed algorithm is its ability to avoid the undesirable high switching frequency for high- and medium- voltage stages despite the fact that the inverter's dc sources voltages are selected to maximize the number of levels by state redundancy elimination. The high- and medium- voltage stages switching algorithms have been developed to assure fundamental switching frequency operation of the high voltage stage and not more than few times this frequency for the medium voltage stage. The low voltage stage is controlled using a SVPWM to achieve the reference voltage vector exactly and to set the order of the dominant harmonics. The inverter has been constructed and the control algorithm has been implemented. Test results show that the proposed algorithm achieves the desired features and all of the major hypotheses have been verified.

• Journal of Power Electronics
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• v.11 no.3
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• pp.271-278
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• 2011

This paper presents a LLC resonant controller IC for secondary side control without external active devices to achieve low profile and low cost LED back light units. A gate driving transformer is adopted to isolate the primary side and the secondary side instead of an opto-coupler. A new integrated dimming circuitry is proposed to improve the dynamic current control characteristic and the current density of a LED for the brightness modulation of a large screen LCD. A dual-slope clock generator is proposed to overcome the frequency error due to the under shoot in conventional approaches. This chip is fabricated using 0.35 ${\mu}m$ BCD technology and the die size is $2{\times}2\;mm^2$. The frequency range of the clock generator is from 50 kHz to 500 kHz and the range of the dead time is from 50 ns to 2.2 ${\mu}s$. The efficiency of the LED driving circuit is 97 % and the current consumption is 40 mA for a 100 kHz operation frequency from a 15 V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.950-956
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• 1986

In this paper, a direct addressing mode of a microprocessor is introduced to save memory capacity, and also a dedicated digital filter is constructed to speed up the filter processing and to enable an easy selection of the impulse response types. A theoretical analysis has been conducted on the errors caused by the finite word klength, rounding-off and multiplication procedures. The digital filter designed by the proposed method is made into a module which can function as a 7th-order recursive or a 14-order nonrecursive type with a simples witch operation. The proposed filter is implemented on a printed-circuit board. The frequency characteristics of this filter can be controlled by the multiplication values stored in ROMs. A low-pass, a high-pass and a band-pass filter have been designed and their frequency characteristics are verified by actual measurements. For a order higher filer, two filter modules have been cascaded into an integrated filter of 23rd-order non-recursive low-pass type and a 12th-order recursive multiband type. Their frequency characteirstics have been found to agree with the theory.