Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of a 2.5GHz CMOS PLL Frequency Synthesizer Using a High-Speed Low-Power Prescaler

고속 저전력 프리스케일러를 사용한 2.5GHz CMOS PLL 주파수합성기 설계

  • Kang, K.S. (Department of Electronics Engineering, University of Incheon) ;
  • Oh, G.C. (Department of Electronics Engineering, University of Incheon) ;
  • Lee, J.K. (Department of Electronics Engineering, University of Incheon) ;
  • Park, J.T. (Department of Electronics Engineering, University of Incheon) ;
  • Yu, C.G. (Department of Electronics Engineering, University of Incheon)
  • Published : 2005.11.26
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Abstract

This paper describes a PLL frequency synthesizer for wireless LNA applications. The design is focused mainly on low-power and low-phase noise characteristics. A 128/129 dual-modulus prescaler has been designed using the proposed TSPC D flip-flops for high-speed operation and low-power consumption The designed synthesizer includes all building blocks for elimination of external components, other than the crystal. Its operating frequency can be programmed by external data. The frequency synthesizer has been designed using a $0.25{\mu}m$ CMOS process parameters. It operates in the frequency range of 2GHz to 3GHz and consumes 3.2mA at 2.5GHz from a 2.5V supply.

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