• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.9
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• pp.671-676
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• 2012

In this paper, TCAD assessment of 30-V class n-channel EDMOS (extended drain metal-oxide-semiconductor) transistors with DWFG (dual work function gate) structure are described. Gate of the DWFG EDMOS transistor is composed of both p- and n-type doped region on source and drain side. Additionally, lengths of p- and n-type doped gate region are varied while keeping physical channel length. Two-dimensional device structures are generated trough TSUPREM-4 and their electrical characteristics are investigated with MEDICI. The DWFG EDMOS transistor shows improved electrical characteristics than conventional device - i.e. higher transconductance ($g_m$), better drain output current ($I_{ON}$), reduced specific on-resistances ($R_{ON}$) and higher breakdown characteristics ($BV_{DSS}$).

• Journal of the Korean GEO-environmental Society
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• v.16 no.11
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• pp.39-43
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• 2015

In this study, the infiltration quantity of fine-grained soil into coarse-grained soil or aggregate for methods to accelerate consolidation drainage is checked by laboratory tests under various conditions and those characteristics on infiltration are examined closely. Irrespectively of pressures to fine-grained soil corresponding to stresses in a soil mass or moisture contents of fine-grained soil, fine-grained soil does not infiltrate into standard sand and marine sand, so it is verified that drain-resistance into sand mass of drainage / pile does not occur entirely and its shear strength would increase highly by water compaction. It is known that the infiltration depth of fine-grained soil into aggregate increases according that those size is larger in case of aggregates and it increases according that the pressure or the moisture contents is higher in case of same size aggregate. It is thought that drain-resistance into aggregate mass of drainage / pile would occurs by infiltrated fine-grained soil in advance though the infiltration depth of fine-grained soi of lower moisture content than liquid limit into 13 mm aggregate is low quietly. So gravel drain method or gravel compaction pile method, etc. using aggregate of gravels or crushed stones, etc. larger than sand particle size should be not applied in very soft fine-grained soil mass of higher natural moisture contents than liquid limit, and it is thought that its applying is not nearly efficient also in soft fine-grained soil mass of lower natural moisture contents than liquid limit.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.133-133
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• 2008

Recently, as the down-scailing of field-effect transistor devices continues, Schottky-barrier field-effect transistors (SB-FETs) have attracted much attention as an alternative to conventional MOSFETs. SB-FETs have advantages over conventional devices, such as low parasitic source/drain resistance due to their metallic characteristics, low temperature processing for source/drain formation and physical scalability to the sub-10nm regime. The good scalability of SB-FETs is due to their metallic characteristics of source/drain, which leads to the low resistance and the atomically abrupt junctions at metal (silicide)-silicon interface. Nevertheless, some reports show that SB-FETs suffer from short channel effect (SCE) that would cause severe problems in the sub 20nm regime.[Ouyang et al. IEEE Trans. Electron Devices 53, 8, 1732 (2007)] Because source/drain barriers induce a depletion region, it is possible that the barriers are overlapped in short channel SB-FETs. In order to analyze the SCE of SB-FETs, we carried out systematic studies on the Schottky barrier overlapping in short channel SB-FETs using a SILVACO ATLAS numerical simulator. We have investigated the variation of surface channel band profiles depending on the doping, barrier height and the effective channel length using 2D simulation. Because the source/drain depletion regions start to be overlapped each other in the condition of the $L_{ch}$~80nm with $N_D{\sim}1\times10^{18}cm^{-3}$ and $\phi_{Bn}$ $\approx$ 0.6eV, the band profile varies as the decrease of effective channel length $L_{ch}$. With the $L_{ch}$~80nm as a starting point, the built-in potential of source/drain schottky contacts gradually decreases as the decrease of $L_{ch}$, then the conduction and valence band edges are consequently flattened at $L_{ch}$~5nm. These results may allow us to understand the performance related interdependent parameters in nanoscale SB-FETs such as channel length, the barrier height and channel doping.

• Korean Journal of Agricultural Science
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• v.25 no.2
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• pp.225-234
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• 1998

This study was compared the degree of consolidation by Hyperbolic, Curve fitting, Asaoka's, Monden's methods using measured value with theoretical curve in consideration of smear effect and well resistance. The results of the study were summarized as follows ; 1. The degree of consolidation by Hyperbolic method was underestimated than the degree of consolidation by Curve fitting, Asaoka's, and Monden's methods. 2. Typical range of horizontal coefficient of consolidation was $C_h=(2{\sim}3)C_v$ in the case considering smear effect and well resistance, and $C_h=(0.5{\sim}2.5)C_v$ in the case disregarding smear effect and well resistance. 3. The degree of consolidation obtained by ground settlement monitoring was nearly same value when the coefficient of permeability of smear zone by back analysis was shown the half that of in-situ and the diameter of smear zone was shown double that of mendrel. 4. Increasing of diameter reduction ratio of drain, the time of consoildation was delayed. The affection of well resistance the case of small coefficient of permeability was much more than that in the case of large coefficient of permeability. It was recommended that design of diameter reduction of drain consider smear effect and well resistance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.49-54
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• 1990

In this paper, a simple model is presented for the gate-voltage dependence of the parasitic resistance in MOSFETs with the lightly-doped drain (LDD) structure. At the LDD region located under the gate electrode, an accumulation layer is formed due to the gate voltage. The parasitic resistance of the source side LDD in the channel is treated as a parallel combination of the resistance of the accumulation layer and that of the bulk LDD, which is approximated as a spreading resistance from the end of the channel inversion layer to the ${n^+}$/LDD junction boundary. Also the effects of doping gradients at the junction are discussed. As result of the model, the LDD resistance decreases with increasing the gate voltage at the linear regime, and increase quasi-linearly with the gate voltage at the saturation regime, considering th velocity saturation both in the channel and in the LDD region. The results are in good agreement with experimental data reported by others.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.287-294
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• 2011

In this paper, two competing mechanisms determining drain current of tunneling field-effect transistors (TFETs) have been investigated such as band-to-band tunneling and drift. Based on the results, the characteristics of TFETs have been discussed in the tunneling-dominant and drift-dominant region.

• Proceedings of the Korean Geotechical Society Conference
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• 1995.10a
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• pp.1.3-20
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• 1995

The use of band drains for ground improvement has been increased throughout the world during the past 15 years. Apart from other ground improvement techniques, the quality of band drains affects greatly the well resistance of drains, discharge capacity and clogginf tests for four drains selected are carried out and quality is examined.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.157-157
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• 2008

As the minimum feature size of semiconductor devices scales down to nano-scale regime, ultra shallow junction is highly necessary to suppress short channel effect. At the same time, Ni-silicide has attracted a lot of attention because silicide can improve device performance by reducing the parasitic resistance of source/drain region. Recently, further improvement of device performance by reducing silicide to source/drain region or tuning the work function of silicide closer to the band edge has been studied extensively. Rare earth elements, such as Er and Yb, and Pd or Pt elements are interesting for n-type and p-type devices, respectively, because work function of those materials is closer to the conduction and valance band, respectively. In this paper, we increased the work function between Ni-silicide and source/drain by using Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. We demonstrated that it is possible to control the barrier height of Ni-silicide by adjusting the thickness of Pd layer. Therefore, the Ni-silicide using the Pd stacked structure could be applied for high performance PMOSFET.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.28 no.5C
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• pp.313-320
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• 2008

The discharge capacity testing apparatus using penetration method, being able to simulate in laboratory the condition of embedding plastic board drains in field, was developed to investigate consolidation characteristics of ground and to figure out discharge capacity of drains. The developed apparatus with a mandrel and penetrating device was designed to insert PBD into the ground prepared by previously applied pressure, being different from the conventional testing method that the drain was installed and the ground material was poured subsequently. Discharge capacity tests with the conventional apparatus as well as the newly developed one were performed to assess the applicability of the latter. As a result of tests, the conventional method showed delayed consolidation due to overall disturbance of ground and local deformation of drain caused by inhomogeneity of ground. Therefore discharge capacity of drain with the conventional apparatus was measured more or less larger than the expected values whereas discharge capacity with new one could be measured similar to the actual value in field.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.39-48
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• 2016

In this paper, we propose thermal resistance compact model of FinFET structure that has hexagon shaped source/drain. The heating effect and thermal properties were increased by reduced size of the device, and thermal resistance is an important factor to analyze the effect and the properties. The heat source and each contact that is moved heat out were set up in transistor, and domain is divided by the heat source and the four parts of contacts : source, drain, gate, substrate. Each contact thermal resistance model is subdivided as a easily interpretable structure by analyzing the temperature and heat flow of the TCAD simulation results. The domains are modeled based on an integration or conformal mapping method through the structure parameters according to its structure. First modeled by analyzing the thermal resistance to a single fin, and applying the change in the parameter of the channel increases to improve the accuracy of the thermal resistance model of the multi-fin/ finger. The proposed thermal resistance model was compared to the thermal resistance by analyzing results of the 3D Technology CAD simulations, and the proposed total thermal resistance model has an error of 3 % less in single and multi-finl. The proposed thermal resistance model can predict the thermal resistance due to the increase of the fin / finger, and the circuit characteristics can be improved by calculating the self-heating effect and thermal characterization.