• 한국지반공학회지:지반
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• 제8권1호
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• pp.67-80
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• 1992

본 연구에서는 시간에 따른 공사하중의 크기 변화가 다양할 경우에, smear zone및 well resistance의 영향을 모두 고려하여 설계시에 요구되는 모래기등 영향원의 반지름(즉, 모래기둥의 설치간격)을 결정하기 위한 해석법을 제시하였다. 이를 위해 단순선형점증하중의 경우에 대해 제시된 Olson의 해석법(smear zone 및 well resistance의 영향을 모두 무시한 경우)을 변형하였으며, 아울러 제시된 해석법을 토대로 설계에 관련된 여러가지 변수가 모래기end의 설치간격에 미치는 영향을 조건별로 분석하였다.

• 전자공학회논문지A
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• 제30A권9호
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• pp.38-45
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• 1993

In this study, the degradation characteristics of drain output resis-tance was described due to hot electron effects. An semi-empirical model for the degraded drain output resistance was derived from the measured device characteristics. The suggested model was verified from the measured data and the device parameter dependence was also analyzed. The degradation of drain output resistance was increased with stress time and had linear relationship with the degradation of drain current. The device lifetime which was defined by failure criteria of drain output resistance (such as $\Delta$ro/roo=5%) was equivalent to that of failure criteria of drain current (such as $\Delta$ID/ID=5%)

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2010년도 춘계 학술발표회
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• pp.1256-1263
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• 2010

Suction Drain Method is soft ground improvement technique, in which a vacuum pressure can be directly applied to the Vertical Drain Board to promote consolidation and strengthening the soft ground. This method does not require a surcharge load, different to embankment or Preloading Method. In this study, ground improvement efficiency of suction drain method was estimated when duplex loading pressure with vacuum and pressure. During suction drain method process, surface settlement and pore pressure were monitored, and cone resistance test as well as water content were also measured after the completion of Suction Drain Method treatment.

• 한국농공학회:학술대회논문집
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• 한국농공학회 1998년도 학술발표회 발표논문집
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• pp.438-443
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• 1998

In this study, compared the degree of consoildation of vertical drain considering variation of smear effect and well resistance with that of hyperbolic and curve fitting method. It applied Barren, Yoshikuni, Hansbo, Onoue's theory for the consolidation of vertical drain, and compared differences of theoretical curve by comparing with measured value, and finded out the extent of smear effect and well resistance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1797-1799
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• 2000

A SOI LDMOS with trench drain and graded gate is proposed to improve the on resistance. The proposed structure can decrease the on resistance by reducing the path of electron current. Simulation results by SUPREM and MEDICI have shown that the on resistance of the LDMOS with trench drain and graded gate was 14.8 % lower than conventional LDMOS with graded gate.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.208-211
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• 1999

Abstract - Electrical characteristics or asymmetric n-MOSFET's with different source and drain geometry are experimently investigated using test structures having various gate width. Saturation drain current and resistance in linear region are estimated by a simple schematic model, which consists of conventional device having parasitic resistor. A comparison of experimental results of symmetric and asymmetric devices gives the parasitic resistance caused by abnormal device structure. The suggested model shows good agreement with the measured drain current for both forward- and reverse-modes.

• 전자공학회논문지
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• 제50권10호
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• pp.67-75
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• 2013

본 논문에서는 RSD(Raised Source/Drain)구조를 가지는 FinFET에서 3차원적 전류 흐름을 고려한 소스와 드레인의 해석적 저항모델을 제시한다. FinFET은 Fin을 통해 전류가 흐르기 때문에 소스/드레인의 기생저항이 크고 채널을 포함한 전체저항에서 중요한 부분을 차지한다. 제안하는 모델은 3차원적 전류흐름을 고려하여 contact부터 channel 직전 영역까지의 소스/드레인 저항을 나타내며 contact저항과 spreading저항의 합으로 이루어져 있다. Contact저항은 전류의 흐름을 고려한 가이드라인을 통해 작은 저항의 병렬합으로 모델링되고 spreading저항은 적분을 통해 구현했다. 제안된 모델은 3D numerical solver인 Raphael의 실험결과를 통해 검증했다. 본 연구에서 제안된 기생저항 모델을 BSIM-CMG와 같은 압축모델에 구현하여 DC 및 AC 성능 예측의 정확도를 높일 수 있을 것이다.

• E2M - 전기 전자와 첨단 소재
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• 제8권5호
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.533-536
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• 1998

The electrical characteristics of NMOSFETs with asymmetrical source/drain regions have been expermentally investigated using test devices fabricated by $0.35\mu\textrm{m}$ CMOS technology. The performance degradation for asymmetric transistor and its causes are analyzed. The parasitic resistances, such as series resistance of active regions and silicide junction contact resistance, are distributed in parallel along the channel. Depending on source/drain geometry, the array of those resistances is changed, that results the various electrical properties.

• 전기학회논문지
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• 제57권2호
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• pp.235-238
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• 2008

This paper explores 28 nm MOSFET design for LSTP(Low Standby Power) applications using TCAD(Technology Computer Aided Design) simulation. Simulated results show that the leakage current of the MOSFET is increasingly dominated by GIDL(Gate Induced Drain Leakage) instead of a subthreshold leakage as the Source/Drain extension doping increases. The GIDL current can be reduced by grading lateral abruptness of the drain at the expense of a higher Source/Drain series resistance. For 28 nm MOSFET suggested in ITRS, we have shown Source/Drain design becomes even more critical to meet both leakage current and performance requirement.