• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.469-472
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• 1987

The hot-carrier induced degradation in very short-channel MOSFET was studied systematically. Under the traditional DC stress conditions, the threshold voltage shift (${\Delta}Vt$) and the transconductance degradation (${\Delta}Gm$/(Gmo-${\Delta}Gm$)) were confirmed to depend exponentially on the stress time and the dependency between the two parameters was proved to be linear. And the degradation due to the DC stress across gate and drain was studied. As the AC dynamic process is more realistic in actual device operation, the effects of dynamic stresses were studied.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.339-343
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• 1999

This paper reports the characteristics of poly-Si TFT unitary CMOS circuits fabricated with various techniques, in order to investigate the optimum process conditions. The active films were deposited by PECVD and LPCVD using $SiH_4\; and\; Si_2H_6$ as source gas, and annealed by SPC and ELA methods. The impurity doping of the oource and drain electrodes was performed by ion implantation and ion shower. In order to investigate the AC characteristics of the poly-Si TFTs processed with various methods, we have examined the current driving characteristics of the polt-Si TFT and the frequency characteristics of 23-stage CMOS ring oscillators. Ithas been observed that the circuits fabricated using $Si_2H_6$ with low-temperature process of ELA exhibit high switching speed and current driving performances, thus suitable for real application of large area electronics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.86-90
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• 1992

We have studied the characteristics of n-and p-channel FETs with submicron channel length fabricated by twin-well process. Threshold voltage variation and potential distribution with channel ion implantation conditions and impurity profile of n-and p-channel region wee simulated using SUPREM-II and MINIMOS 4.0 simulater, P-channel FET had buried-channel in the depth of 0.15 $\mu\textrm{m}$ from surface by counter-doped boron ion implantation for threshold voltage adjustment. As a result of device measurement, we have obtained good drain saturation characteristics for 3.3 [V] opreation, minimized short channel effect with threshold voltage shift below 0.2[V], high punchthrough and breakdown voltage above 10[V] and low subthreshold value.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.59-62
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• 2000

A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density, stress current, transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width$\times$length 10$\times$1${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gave unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.5
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• pp.347-352
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• 1998

In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.105-110
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• 2008

We have proposed a new structure of poly-silicon thin film transistor(TFT) which was fabricated the LDD region using doping oxide with graded spacer by etching shape retio. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $HT_2$/plasma processes are fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring /analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si Brain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplity of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Journal of the Korean GEO-environmental Society
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• v.13 no.8
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• pp.85-94
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• 2012

Evaluation of the smear effect caused by mandrel penetration into soft ground for a vertical drain installation is very important to predict the consolidation time of soft ground improvement. 30 kinds of laboratory model tests considering in situ conditions were conducted to investigate the formation of a smear zone and the decrease of coefficient of permeability in the disturbed zone. Three types(C(clay):M(silt)=1:1, 0.5:0.5, and 0:1) of reconstituted samples were used for 3 dimensional smear zone test. An experimental study was performed focusing on length of mandrel penetration, mandrel shape and size, earth pressure, and ground condition(unit weight and grain size distributions). Laboratory test results show that the length of mandrel penetration is the most critical factor for the formation of smear zone. As a result, the ratio between diameter of the smear zone($d_s$) and that of mandrel($d_m$) at field using long mandrel becomes larger than conventional $d_s/d_m$. The ratio between $d_s$ and $d_m$ ranges from 1.89 and 2.48 with the sample at C:M=1:0. It was also found that the $d_s/d_m$ value with the round shape of the mandrel is smaller than that of diamond one. The value of $d_s/d_m$ decreased with larger mandrel size, lower unit weight, and higher earth pressure. However, higher silt content led to increase of $d_s/d_m$. The ratio between coefficient of horizontal permeability in the smear zone($k_{hs}$) and that of undisturbed zone($k_{ho}$) ranged from 0.70 to 0.85. The test results imply that factors and values affecting $k_{hs}/k_{ho}$ show similar tendency with $d_s/d_m$.

• Journal of Korea Water Resources Association
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• v.52 no.3
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• pp.227-234
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• 2019

The vulnerability of urban disasters is increased with the rapid urbanization and industrialization, and the extreme rainfall event is increased due to the global climate change. Urban inundation is also increased due to the extreme rainfall event beyond the capacity limit of facility for the damage prevention. The underground detention vault and the underground drain tunnel are rapidly being utilized to prevent urban inundation. Therefore, the hydraulic review and design analysis of the inlet of the underground facility are important. In this study, the water level of the approach flow according to the inflow discharge is measured and the flow characteristic of the inlet (tangential and spiral) is analyzed. For the spiral inlet, the multi-stage is introduced at the bottom of the inlet to improve the inducing vortex flow at low discharge conditions. In case of the tangential inlet, the discharging efficiency is decreased rapidly with hydraulic jump in the high flow discharge. The rising ratio of the water level in the multi-stage spiral inlet is higher than the tangential inlet, but the stable discharging efficiency is maintained at low and high discharge conditions. And the empirical formula of water level-flow discharge is derived in order to utilize inlets used in this study.

• ETRI Journal
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• v.34 no.6
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• pp.950-953
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• 2012

Schottky barrier single electron transistors (SB-SETs) and Schottky barrier single hole transistors (SB-SHTs) are fabricated on a 20-nm thin silicon-on-insulator substrate incorporating e-beam lithography and a conventional CMOS process technique. Erbium- and platinum-silicide are used as the source and drain material for the SB-SET and SB-SHT, respectively. The manufactured SB-SET and SB-SHT show typical transistor behavior at room temperature with a high drive current of $550{\mu}A/{\mu}m$ and $-376{\mu}A/{\mu}m$, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB-SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is $0.05{\mu}S$ and $1.2{\mu}S$ for the SB-SET and SB-SHT, respectively. In the SB-SET and SB-SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB-SET and SB-SHT can be operated as a conventional field-effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.

• Journal of the Korean Institute of Rural Architecture
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• v.1 no.2
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• pp.83-96
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• 1999

The Buildings and facilities of municipal Councils of fundamental autonomous organization in various regions were made on the basis of its experiences in 1950s but lacked constructional sophistication and failed to comprehend their functions, resulting in several repairs and renovations after the dedications of the buildings. They also undermined the efficiencies of the worn and was a big drain on the budget of municipal councils. Furthermore, especially after the integration of rural and urban areas. Municipal councils in urban areas couldn't accommodate the increased staffs. Thereby, They used the established councils in the cities and countries and repaired and renovated other buildings of which were permitted as offices, decreasing the eligibility of the buildings for municipal councils. The poor constructional working conditions triggered new constructions of the buildings reserved only for municipal councils. The study finds out find out about the work of municipal councils and analyzes how the municipal council buildings are used as substitutional spaces, directing which way they should go in mapping out spaces. Resultantly, It becomes basic materials in constructing municipal buildings.