• Title/Summary/Keyword: double-low

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Thermal performance evaluation of Temperable Low-e glass window through Heating Energy consumption Analysis (난방에너지 사용량 분석을 통한 후강화 로이유리 창호의 단열성능 평가)

  • Jang, Cheol-Yong;Kim, Jeong-Gook;Ahn, Byung-Lip;Kim, Jun-Sup;Haan, Chan-Hoon
    • 한국태양에너지학회:학술대회논문집
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    • 2012.03a
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    • pp.200-205
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    • 2012
  • In the high oil price age, intensification of energy efficiency promotion in the building sector is required. Windows are dominating in large percent of whole building loads, and are regarding as the primary target of energy efficiency. In this study, in order to reduce heat loss of buildings, we investigate the thermal performance properties of Temperable Low-e glazing coated Ag membrane that has high electrical conductivity. The Temperable Low-e glazing windows has high insulation and shading properties, and it has strength that can supply various product which consumers want. In order to evaluate thermal performance of temperable windows, we install single low-e windows and double low-e windows in the experimental chamber and analysis the comparison heating energy consumption between single and double Low-e glazing windows. performance evaluation was conducted.

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Low Cost and High Performance Single Phase UPS Using a Single-Loop Robust Voltage Controller

  • Ji, Jun-Keun;Ku, Dae-Kwan;Lim, Seung-Beom
    • Journal of Power Electronics
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    • v.15 no.3
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    • pp.695-701
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    • 2015
  • Uninterruptible Power Supplies (UPSs) can be largely divided into the passive-standby, line-interactive and double-conversion methods. This paper proposes a double-conversion UPS with a low cost and high performance. This single phase UPS uses a single-loop robust voltage controller and 1-switch voltage doubler strategy PFC. The proposed UPS is composed of a single phase PFC, a half-bridge inverter, a battery charger and a battery discharger. Finally, the validity of proposed UPS was verified by various experimental tests.

Dielectric Properties and a Equivalent Circuit of ZnO-Based Varistor (ZnO 바리스터의 유전특성과 등기회로)

  • Rho, Il-Soo;Kang, Dae-Ha
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.12
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    • pp.2166-2172
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    • 2007
  • In this study a low-signal equivalent circuit based on the Double Schottky Barrier model is proposed for ZnO-based varistor. Since pin-lead inductance and stray capacitance are considered in pin-lead type ZnO varistor these inductance and capacitance could be removed from the experimental dielectric data of the varistor. According to the equivalent circuit simulation results the higher the varistor-voltage of varistor sample the capacitance of dielectric layer is larger, and the capacitances of semiconducting layer and depletion layer are smaller, while the parallel resistances of semiconducting layer and depletion layer are more larger values. Spectra of the dielectric loss factor $tan{\delta}$ show 2 peaks in low frequency and high frequency regions respectively. The low-frequency peak is due to the relaxation by deep donors and the high-frequency peak is due to the relaxation by shallow donors. Above results are well consistent with the theoretical mechanism of ZnO varistor.

A Low-Loss Patch LTCC 60 GHz BPF Using Double Patch Resonators

  • Lee, Young Chul
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.570-572
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    • 2012
  • In this paper, a three-dimensional (3-D) low-loss and wide-band BPF based on low-temperature co-fired ceramic (LTCC) has been presented for mm-wave wireless communication applications. The proposed BPF is designed in a 6-layer LTCC substrate. The double patch resonators are fully integrated into the LTCC dielectrics and vertical via and planar CPW transitions are designed for interconnection between embedded resonators and in/output ports and MMICs, respectively. The designed BPF was fabricated in a 6-layer LTCC dielectric. The fabricated BPF shows a centre frequency (fc) of 53.23 GHz and a 3dB bandwidth of 14.01 % from 49.5 to 56.9 GHz (7.46 GHz). An insertion loss of -1.56 dB at fc and return losses below -10 dB are achieved. Its whole size is $4.7{\times}1.7{\times}0.684mm^3$.

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Fabrication of High Performance and Low Power Readout Integrated Circuit for $320{\times}256$ IRFPA ($320{\times}256$ 초점면배열 적외선 검출기를 위한 고성능 저 전력 신호취득회로의 제작)

  • Kim, Chi-Yeon
    • Journal of the Korea Institute of Military Science and Technology
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    • v.10 no.2
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    • pp.152-159
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    • 2007
  • This paper describes the design, fabrication, and measurement of ROIC(ReadOut Integrated Circuit) for $320{\times}256$ IRFPA(InfraRed Focal Plane Array). A ROIC plays an important role that transfer photocurrent generated in a detector device to thermal image system. Recently, the high performance and low power ROIC adding various functions is being required. According to this requirement, the design of ROIC focuses on 7MHz or more pixel rate, low power dissipation, anti-blooming, multi-channel output mode, image reversal, various windowing, and frame CDS(Correlated Double Sampling). The designed ROIC was fabricated using $0.6{\mu}m$ double-poly triple-metal Si CMOS process. ROIC function factors work normally, and the power dissipation of ROIC is 33mW and 90.5mW at 7.5MHz pixel rate in the 1-channel and 4-channel operation, respectively.

The properties of copper films deposited by RF magnetron sputtering (RF 마그네트론 스퍼터링법에 의해 증착된 구리막의 특성)

  • 송재성;오영우
    • Electrical & Electronic Materials
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    • v.9 no.7
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    • pp.727-732
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    • 1996
  • In the present paper, the Cu films 4.mu.m thick were deposited by RF magnetron sputtering method on Si wafer. The Cu films deposited at a condition of 100W, 10mtorr exhibited a low electrical resistivity of 2.3.mu..ohm..cm and densed microstructure, poor adhesion. The Cu films grown by 200W, 20mtorr showed a good adhesion property and higher electrical resistivity of 7.mu..ohm..cm because of porous columnar microstructure. Therefore, The Cu films were deposited by double layer deposition method using RF magnetron sputtering on Si wafer. The dependence of the electrical resistivity, adhesion, and reflectance in the CU films [C $U_{4-d}$(low resistivity) / C $U_{d}$(high adhesion) / Si-wafer] on the thickness of d has been investigated. The films formed with this deposition methods had the low electrical resistivity of about 2.6.mu..ohm..cm and high adhesion of about 700g/cm.m.m.

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Ultra-Low Powered CNT Synaptic Transistor Utilizing Double PI:PCBM Dielectric Layers (더블 PI:PCBM 유전체 층 기반의 초 저전력 CNT 시냅틱 트랜지스터)

  • Kim, Yonghun;Cho, Byungjin
    • Korean Journal of Materials Research
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    • v.27 no.11
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    • pp.590-596
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    • 2017
  • We demonstrated a CNT synaptic transistor by integrating 6,6-phenyl-C61 butyric acid methyl ester(PCBM) molecules as charge storage molecules in a polyimide(PI) dielectric layer with carbon nanotubes(CNTs) for the transistor channel. Specifically, we fabricated and compared three different kinds of CNT-based synaptic transistors: a control device with $Al_2O_3/PI$, a single PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%), and a double PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%)/PI:PCBM(0.05 wt%). Statistically, essential device parameters such as Off and On currents, On/Off ratio, device yield, and long-term retention stability for the three kinds of transistor devices were extracted and compared. Notably, the double PCBM device exhibited the most excellent memory transistor behavior. Pulse response properties with postsynaptic dynamic current were also evaluated. Among all of the testing devices, double PCBM device consumed such low power for stand-by and its peak current ratio was so large that the postsynaptic current was also reliably and repeatedly generated. Postsynaptic hole currents through the CNT channel can be generated by electrons trapped in the PCBM molecules and last for a relatively short time(~ hundreds of msec). Under one certain testing configuration, the electrons trapped in the PCBM can also be preserved in a nonvolatile manner for a long-term period. Its integrated platform with extremely low stand-by power should pave a promising road toward next-generation neuromorphic systems, which would emulate the brain power of 20 W.

Geometry optimization of a double-layered inertial reactive armor configured with rotating discs

  • Bekzat Ajan;Dichuan Zhang;Christos Spitas;Elias Abou Fakhr;Dongming Wei
    • Advances in Computational Design
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    • v.8 no.4
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    • pp.309-325
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    • 2023
  • An innovative inertial reactive armor is being developed through a multi-discipline project. Unlike the well-known explosive or non-explosive reactive armour that uses high-energy explosives or bulging effect, the proposed inertial reactive armour uses active disc elements that is set to rotate rapidly upon impact to effectively deflect and disrupt shaped charges and kinetic energy penetrators. The effectiveness of the proposed armour highly depends on the tangential velocity of the impact point on the rotating disc. However,for a single layer armour with an array of high-speed rotating discs, the tangential velocity is relatively low near the center of the disc and is not available between the gap of the discs. Therefore, it is necessary to configure the armor with double layers to increase the tangential velocity at the point of impact. This paper explores a multi-objective geometry design optimization for the double-layered armor using Nelder-Mead optimization algorithm and integration tools of the python programming language. The optimization objectives include maximizing both average tangential velocity and high tangential velocity areas and minimizing low tangential velocity area. The design parameters include the relative position (translation and rotation) of the disc element between two armor layers. The optimized design results in a significant increase of the average tangential velocity (38%), increase of the high tangential velocity area (71.3%), and decrease of the low tangential velocity area (86.2%) as comparing to the single layer armor.

The Estimation of Heating, Cooling Load and Economical Efficiency Analysis of Insulation Paint Coating Windows (단열 도료 코팅 창호의 냉난방부하 특성분석 및 경제성 평가)

  • Jeong, Yeol-Wha;Kim, Byoung-Soo
    • Journal of the Korean Solar Energy Society
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    • v.31 no.6
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    • pp.95-102
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    • 2011
  • The purpose of study is to estimate heating, cooling load performance and economic efficiency in office building with applied the functional paint. this paint can reduced SHGC(Solar Heat Gain Coefficient) on the glazing surface by coating. In this study, estimated to compared with double glazing, low-e glazing, IP(Insulation Paint) and IPu(Insulation UV-Cut Paint) coating glazing. As a result of this study, 1)heating & cooling load Analysis, SHGC value and U-factor of double glazing is about 0.70 and 3.29($W/m^2K$). low-E glazing is about 0.65 and 2.70($W/m^2K$). Two-side it is about 0.27 and 3.25($W/m^2K$). When compared to double glazing, annual heating & cooling load of low-E glazing, Two-side IPu and IP paint coating glazing is 3,012MWh($124kWh/m^2$), 2,910MWh($120kWh/m^2$), 2,867MWh($118.4kWh/m^2$) and 2,867MWh($118.4kWh/m^2$). It i sreduced to 2.0%, 5.2%, 6.7%, and 6.7% respectively. 2)the estimation of economic efficiency, low-e glazing installed in office building can not recover the investment within a lifetime 40years. but IPu and IP paint, two-side coating in glazing, have a payback period of 13 years respectively.

Survey evaluation of thermal boundary condition in the inside and outside of double skin facade

  • Shin, Hyun-Cheol;Jang, Gun-Eik
    • KIEAE Journal
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    • v.15 no.4
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    • pp.29-35
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    • 2015
  • Purpose: Double skin facade is a representative advantageous passive technology of building skin in the aspect of energy saving and environment improvement, reduces heat loss with buffer space in winter season and enhances indoor air and comfort of residents by activating natural ventilation in mid-season. However, in summer season, temperature increase in the intermediate space due to solar energy from exterior transparent skin could be a potential problem; also, relatively weak buoyancy of air caused by low density difference between double-skin facade could increase cooling load as air of intermediate space in high temperature hangs. However, proof data is insufficient to objectify such phenomenon. Method: In this study, researchers surveyed air temperature of intermediate space and airflow and diagnosed its cause targeting on applied multistory facade in the building which gives thermal uncomfort to residents. Also, the researchers produced Solar-air heat transfer coefficient meter, measured thermal boundary condition of double-skin facade, and presented the result of measurement as an objectified verification material regarding overheating phenomenon in the intermediate space of double-skin facade in summer season. Result: Inefficient condition was verified that total heat increases and overheating due to insufficient natural ventilation in multistory facade. In addition, logic behind preceding research was objectified and verified regarding high temperature phenomenon in the intermediate space which could increase cooling load in summer season.