• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.4
• /
• pp.225-232
• /
• 2009

An analytical compact model for the asymmetric lightly doped Double Gate (DG) MOSFET is presented. The model is developed using the Lambert Function and a 2-dimensional (2-D) parabolic electrostatic potential approximation. Compact models of the net charge and channel current of the DG-MOSFET are derived in section 2. Results for the channel potential and current are compared with 2-D numerical data for a lightly doped DG MOSFET in section 3, showing very good agreement.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.3
• /
• pp.479-485
• /
• 2006

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin undoped Si channel for SCEs control, ale being validated for sub-20nm scaling. A novel analytical transport model for the subthreshold mode of DGMOSFETs is proposed in this paper. The model enables analysis of short channel effect such as the subthreshold swing(SS), the threshold voltage roil-off$({\Delta}V_{th})$ and the drain induced barrier lowering(DIBL). The proposed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. An approximative solution of the 2D Poisson equation is used for the distribution of electric potential, and Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The new model is used to investigate the subthreshold characteristics of a double gate MOSFET having the gate length in the nanometer range $(5-20{\sim}nm)$ with ultra thin gate oxide and channel thickness. The model is verified by comparing the subthreshold swing and the threshold voltage roll-off with 2D numerical simulations. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.4
• /
• pp.805-810
• /
• 2016

The dependence of drain induced barrier lowering(DIBL) is analyzed for doping concentration in channel of asymmetric double gate(DG) MOSFET. The DIBL, the important short channel effect, is described as lowering of source barrier height by drain voltage. The analytical potential distribution is derived from Poisson's equation to analyze the DIBL, and the DIBL is observed according to top/bottom gate oxide thickness and bottom gate voltage as well as channel doping concentration. As a results, the DIBL is significantly influenced by channel doping concentration. DIBL is significantly increased by doping concentration if channel length becomes under 25 nm. The deviation of DIBL is increasing with increase of oxide thickness. Top and bottom gate oxide thicknesses have relation of an inverse proportion to sustain constant DIBL regardless channel doping concentration. We also know the deviation of DIBL for doping concentration is changed according to bottom gate voltage.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.4
• /
• pp.804-810
• /
• 2005

An analytical subthreshold swing (SS) model has been presented for double gate MOSFET(DGMOSFET) in this study. The results calculated by this model are more precise for about 10nm channel length and thickness than those derived from the previous models. The results of this model are compared with Medici simulation to varify the validity of this model, and good agreementes have been obtained. The changes of SS have been investigated for various channel lengths, channel thicknesses and gate oxide thicknesses using this model, given that these parameters are very important in design of DGMOSFET. This demonstrates that the proposed model provides useful data for design of nano-scale DGMOSFET. It is Known that the SS is improved to smaller ratios of channel thickness vs channel length and is smaller in very thin oxides. New gate dielectric materials with high permittivity have to be developed to enable design of nano-scale DGMOSFET.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.2
• /
• pp.170-177
• /
• 2008

In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain roll-off widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.9
• /
• pp.2183-2188
• /
• 2014

This paper has analyzed threshold voltage movement for channel doping concentration of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is generally fabricated with low doping channel and fully depleted under operation. Since impurity scattering is lessened, asymmetric DGMOSFET has the adventage that high speed operation is possible. The threshold voltage movement, one of short channel effects necessarily occurred in fine devices, is investigated for the change of channel doping concentration in asymmetric DGMOSFET. The analytical potential distribution of series form is derived from Possion's equation to obtain threshold voltage. The movement of threshold voltage is investigated for channel doping concentration with parameters of channel length, channel thickness, oxide thickness, and doping profiles. As a result, threshold voltage increases with increase of doping concentration, and that decreases with decrease of channel length. Threshold voltage increases with decrease of channel thickness and bottom gate voltage. Lastly threshold voltage increases with decrease of oxide thickness.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.5
• /
• pp.992-997
• /
• 2016

This paper analyzes the deviation of tunneling current for the ratio of top and bottom gate oxide thickness of short channel asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current significantly increases if channel length reduces to 5 nm. This short channel effect occurs for asymmetric DGMOSFET having different top and bottom gate oxide structure. The ratio of tunneling current in off current with parameters of channel length and thickness, doping concentration, and top/bottom gate voltages is calculated in this study, and the influence of tunneling current to occur in short channel is investigated. The analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for the ratio of top and bottom gate oxide thickness in short channel asymmetric DGMOSFET, specially according to channel length, channel thickness, doping concentration, and top/bottom gate voltages.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.3
• /
• pp.657-662
• /
• 2014

This paper has analyzed the subthreshold swings for top and bottom gate voltages of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates. The subthreshold swing, therefore, has to be analyze not only for top gate voltage, but also for bottom gate voltage. In the pursuit of this purpose, Poisson equation has been solved to obtain the analytical solution of potential distribution with Gaussian function, and the subthreshold swing model has been presented. As a result to observe the subthreshold swings for the change of top and bottom gate voltage using this subthreshold swing model, we know the subthreshold swings are greatly changed for gate voltages. Especially we know the conduction path has been changed for top and bottom gate voltage and this is expected to greatly influence on subthreshold swings.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.36 no.2
• /
• pp.129-135
• /
• 2023

An analytical threshold voltage model is presented to observe the change in threshold voltage shift ΔV_th of a junctionless double gate MOSFET using ferroelectric-metal-SiO₂ as a gate oxide film. The negative capacitance transistors using ferroelectric have the characteristics of increasing on-current and lowering off-current. The change in the threshold voltage of the transistor affects the power dissipation. Therefore, the change in the threshold voltage as a function of theferroelectric thickness is analyzed. The presented threshold voltage model is in a good agreement with the results of TCAD. As a results of our analysis using this analytical threshold voltage model, the change in the threshold voltage with respect to the change in the ferroelectric thickness showed that the threshold voltage increased with the increase of the absolute value of charges in the employed ferroelectric. This suggests that it is possible to obtain an optimum ferroelectric thickness at which the threshold voltage shift becomes 0 V by the voltage across the ferroelectric even when the channel length is reduced. It was also found that the ferroelectric thickness increased as the silicon thickness increased when the channel length was less than 30 nm, but the ferroelectric thickness decreased as the silicon thickness increased when the channel length was 30 nm or more in order to satisfy ΔV_th=0.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.372-377
• /
• 2013

This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET has the advantage to reduce the short channel effects as improving the current controllability of gate. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change of the breakdown voltage for gate oxide thickness and channel thickness.