• Title/Summary/Keyword: double-chip 기술

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A VLSI Implementation of Real-time 8$\times$8 2-D DCT Processor for the Subprimary Rate Video Codec (저 전송률 비디오 코덱용 실시간 8$\times$8 이차원 DCT 처리기의 VLSI 구현)

  • 권용무;김형곤
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.15 no.1
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    • pp.58-70
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    • 1990
  • This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

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Implementation of a Shared Buffer ATM Switch Embedded Scalable Pipelined Buffer Memory (가변형 파이프라인방식 메모리를 내장한 공유버퍼 ATM 스위치의 구현)

  • 정갑중
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.5
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    • pp.703-717
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    • 2002
  • This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

Improvement of Particleboard Manufacturing Process and its Properties Using Powdered Tannin Adhesives (분말상 탄닌수지를 이용한 파티클보드 제조기술 및 물성개선)

  • Kang, Seog Goo;Lee, Hwa Hyoung
    • Journal of the Korean Wood Science and Technology
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    • v.32 no.1
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    • pp.80-87
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    • 2004
  • This study was carried out to improve the properties of powdered tannin adhesive(PT) by adding liquid tannin resin(LT) to PT in the manufacture of particleboard. Mixing the LT to PT from 50% to 100% by weight did not show any difference in particleboard properties, but the higher the powdered tannin resin ratio, the lower the properties of the board. The proper ratio of PT to LT was 30:70 for the improvement of PT-particleboard, unless LT lower than 70%. Internal bonding strength was in proportional to the amount of LT. Mixing amino adhesives and PT did not show any improvements in mechanical and physical properties of the board but they only acted as scavenger for the free formaldehyde.Manufacturing particle board with the adhesive of 30:70 (PT:LT) and by using double blender resulted in high-performance products of E0 level of formaldehyde emission with high water resistance (U type; below 12%, M type; below 25%), as well as saving chip drying energy.

Cost-effective assessment of filter media for treating stormwater runoff in LID facilities (비용 효율적 강우유출수 처리를 위한 LID시설의 여재 평가)

  • Lee, Soyoung;Choi, Jiyeon;Hong, Jungsun;Choi, Hyeseon;Kim, Lee-Hyung
    • Journal of Wetlands Research
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    • v.18 no.2
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    • pp.194-200
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    • 2016
  • The impervious surface rate increased by urbanization causes various problems on the environment such as water cycle distortion, heat island effect, and non-point pollutant discharges. The Low Impact Development (LID) techniques are significantly considered as an important tool for stormwater management in urban areas and development projects. The main mechanisms of LID technologies are hydrological and environmental pollution reduction among soils, media, microorganisms, and plants. Especially, the media provides important functions on permeability and retention rate of stormwater runoff in LID facilities. Therefore, this research was performed to assess the pollutant removal efficiency for different types of media such as zeolite, wood chip, bottom ash, and bio-ceramic. All media show high pollutant removal efficiency of more than 60% for particulate materials and heavy metals. Double layered media is more effective in reducing heavy metals by providing diverse sizes of micro-pores and macro-pores compared to the single layered media. The results recommend the use of different sizes of media application is more cost-effective in LID than a single size of media. Furthermore, soluble proportion of total heavy metal in the stormwater is an important component in proper media selection and arrangement.