• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.515-516
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• 2007

A novel design of contious-time filter for direct conversion receiver applications is proposed. The filter supports different modes including GSM, WCDMA. A 5th chebyshev filter is realized in a gm-C filter topology. The filter circuit is implemented in a standard CMOS $0.35{\mu}m$ processing parameter with a supply voltage of 2.5V. The HSPICE results show that the filter has 200KHz and 5MHz cutoff frequency, and each 3.4us and 85.44us gm value.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.162-165
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• 2000

This paper presents the analysis of the effect which DC offsets produced in the direct-conversion receiver system under the AWGN circumstance exercise on the system performance. Then, as a method which improve the system performance by removing the DC offsets, we proposed the plan which can copes with the time variant DC offsets occurrences according to taking accumulation and average through the loop signals which DC offsets are produced.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.638-646
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• 2005

In recent wireless communications, direct conversion transceiver or If sampling SDR-based receivers have being designed as an alternative to conventional transceiver topologies. In direct conversion receiver a.chitectu.e, the 1.equency/phase offset between the RF input signal and the local oscillator signal is a major impairment factor even though the conventional AFC/APC compensates the service deterioration due to the offset. To rover the limited tracking range of the conventional method and effectively aid compensation scheme in terms of I/Q channel imbalances, the frequency/phase offset compensation in RF-front end signal stage is proposed in this paper. In RF-front end, the varying phase offset besides the fixed large frequency/phase offset are corrected by using early-late phase compensator. A more simple frequency and phase tacking function in digital signal processing stage of direct conversion receiver is effectively available by an ingenious frequency/phase offset tracking method in RF front-end stage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.1 s.116
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• pp.15-23
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• 2007

A simple six-port direct conversion QPSK receiver which is made up of a six-port phase correlator, a signal power detector, and I/Q channel signal de-modulator is designed and implemented in this paper. The output phase signals of six-port phase correlator are also analysed. On the basis of $90^{\circ}C$ phase relation among the six-port phase correlator output signals, the QPSK de-modulation circuit is designed by a simple circuit. The six-port phase correlator is made up of $90^{\circ}$ hybrid branch line and power detector. The six-port phase correlator, which is designed in frequency range of 11.7 to 12.0 GHz, gets the phase error characteristics less than $5^{\circ}$. By considering matching network and amplitude balance in the designed fiequency range, the designed six-port direct conversion QPSK receiver demodulates the I and Q signals with performance less than $5^{\circ}$ phase error.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1071-1077
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• 2010

The six-port phase correlator using lumped elements was designed and fabricated in this paper, also the receiving performance of L-band direct conversion receiver using lumped six-port phase correlator element was analyzed. The proposed L-band lumped six-port phase correlator element was composed of a resistive power divider and the twist-wire coaxial cables. The proposed lumped six-port structure provides the small-sized configuration and wide-band characteristics. The performance of the L-band lumped direct conversion receiver structure was measured under the conditions of 1.69 GHz frequency for LO-CW signal and RF-QPSK signal, which are input signals for the lumped six-port phase correlator element. The direct conversion receiving structure using the proposed lumped six-port phase correlator element can recovered the good digital I/Q signal.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.7
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• pp.730-735
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• 2004

This paper describes what brings about DC offset and the impact or the DC offset on the performance or direct-conversion mobile receiver in WCDMA system. The performance degradation of $E_{b}/N_{o}$ due to the DC offset is presented through simulation result. Direct-conversion RF Transceiver which has the function of DC offset control is implemented and then applied to the WCDMA test-bed for the performance evaluation. The receiver performance degradation of $E_{c}/I_{o}$ is evaluated and analyzed by varying DC offset value. The practical test showed the minimum requirement of DC offset value to meet system performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1269-1276
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• 2005

In this paper, Mixer using the direct-conversion method intended to use in front-end of a RF receiver is designed. The direct conversion Mixer is an alternative wireless receiver architecture to the well-established superheterodyne, particularly for high integration, low power, and low cost. It operates at 2.4GHz band, and is designed and simulated with a 0.35um CMOS technology and HSPICE simulator. Layout is implemented with a Mentor IC Station. The 2.4GHz CMOS Mixer employs a modified single-balanced Gilbert Cell with additional MOSFET in the output stages to improve IIP2, which is a standard of linearity in direct conversion receiver. Additional coversion-stages's transconductances are controlled by each MOSFET's physical properties. The HSPICE simulation results show that the 2.4GHz CMOS Mixer has voltage gam of 29dB, IIP2 of 63dBm, respectively. The Mixer also draws 3.5mA from a 3.3V supply.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.16-20
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• 2002

This paper describes the resistive FET mixer with low IF for the 4-Ch DBF(Digital Beam Forming) receiver with LNA(Low Noise Amplifier). This DBF receiver based on the direct conversion method is generally suitable for high-speed wireless mobile communications. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 2.09 ㎓, 2.08 ㎓ and 10㎒, respectively. The RF input power, LO input power and Vgs are used -10㏈m, 6㏈m and -0.4 V, respectively. In the 4-Ch resistive FET mixer with LNA, the measured IF and harmonic components of 10㎒, 20㎒, 2.09㎓ and 4.17㎓ are about -12.5 ㏈m, -57㏈m, -40㏈m and -54㏈m, respectively. The IF output power observed at each channel of 10㎒ is about -12.5㏈m and it is higher 27.5 ㏈m than the maximum harmonic component of 2.09㎓. Each IF output spectrum of the 4-Ch is observed almost same value and it shows a good agreement with the prediction.

• ETRI Journal
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• v.36 no.1
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• pp.12-21
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• 2014

In this paper, we propose a new digital blind in-phase/quadrature-phase (I/Q) mismatch compensation technique for image rejection in a direct-conversion receiver (DCR). The proposed image-rejection circuit adopts DC offset cancellation and a sign-sign least mean squares (LMS) algorithm with a unique step size adaptation both for a fast and precise I/Q mismatch estimation. In addition, several performance-optimizing design considerations related to accuracy, speed, and hardware simplicity are discussed. The implementation of the proposed circuit in an FPGA results in an image-rejection ratio (IRR) of 65 dB, which is the best performance with modulated signals, along with an adaptation time of 0.9 seconds, which is a tenfold increase in the compensation speed as compared to previously reported circuits. The proposed technique will be a promising solution in the area of image rejection to increase both the speed and accuracy of future DCRs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.10
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• pp.1104-1111
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• 2003

The paper presents an algorithm for the compensation of gain and phase imbalances to exist between I-phase and Q-phase signal at direct conversion receiver. We propose a gain and phase imbalances blind equalization compensation algorithm by using variable step-size adaptive loop at direct conversion receiver. The blind equalization schemes have trade-off between convergence speed and jitter effect for the compensation of gain and phase imbalance. We propose the variable step-size adaptive loop method, which varies the loop coefficients according to errors, for recovering these problem. By using variable step-size adaptive loops, we propose to speed up the convergence process and reduce the jitter effect and simulation results show that the algorithm compensates signal loss and speeds up convergence time.