• Journal of IKEEE
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• v.14 no.3
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• pp.190-198
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• 2010

This paper describes a auto focus piezo actuator driver IC for portable digital camera. The 80[V] DC voltage is generated by a DC-DC converter and supplied to power of piezo moving control circuit. The voltage of piezo actuator needs range -20[V] to 80[V] proportional to 1[Vp-p] input control voltages. The dimensions and number of external parts are minimized in order to get a smaller hardware size. IIC(Inter-IC) interface logic is designed for data interface and it makes debugging easy, test for mass productions. The power consumption is around 40[mW] with supply voltage of 3.6[V]. This device has been fabricated in a 0.6[um] double poly, triple metal 100[V] BCD MOS process and whole chip size is 1600*1500 [$um^2$].

• Journal of IKEEE
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• v.14 no.3
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• pp.232-235
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• 2010

A 60GHz active phase shifter with 65nm CMOS is presented by replacing passive switches in switched-line type phase shifter with active ones. Active-switch phase shifter is composed of active-switch blocks and passive delay network blocks. The active-switch phase shifter design is compact compare with the conventional vector-sum phase shifter. Active-switch blocks are designed to accomplish required input and output impedances whose requirements are different whether the switch is on or off. And passive delay network blocks are composed of lumped L,C instead of normal microstrip line to reduce the size of the circuit. An 1-bit phase shifter is fabricated by TSMC 65nm CMOS technology and measurement results present -4dB average insertion loss and 120 degree phase shift at 65GHz.

• Transactions of the Korean Society of Mechanical Engineers
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• v.8 no.2
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• pp.154-161
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• 1984

A modified technique of the transient hot wire method to measure the thermal conductivity of fluid has been described in this paper. The thermal conductivity of fluid can be obtained by acquiring wire temperature as a function of time. Multiplication of the inverse slope of the temperature versus logarithm of time by an instrumental constant gives the thermal conductivity. The constant voltage was applied to Wheatstone bridge circuit. The wire temperature can be measured as a function of time precisely with the aid of the data acquisition system composed of a microprocessor and an analog-digital converter. The thermal conductivity of the electrically conducting fluid has been measured with the insulated hot wire coated by electrically non-conducting material. The effect of the coated insulation layer on the thermal conductivity has been examined, in which it is confirmed that the thermal conductivity of electrically conducting liquid can be determined by the transient coated hot wire method. Thermal conductivities of methanol, carbontetrachrolide, Freon-22 and glycerin have been measured at room temperature in the pressure from 0.1MPa to 35.1MPa. The experiment has been performed to compare the data from the bare and the coated wires, and the results are satisfactory.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.1
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• pp.37-46
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• 2003

The transient responses on arbitrarily interconnected digital transmission lines are analyzed by an efficient node discretization technique. Since the proposed node discretization technique offers an efficient means to discretize transmission lines, the transient waveform at any position on the arbitrarily interconnected lines is easily predicted. Dispersive microstrip multiconductor transmission lines arbitrarily connected are analized for generality. The derivation of frequency-dependent equivalent circuit elements of coupled transmission lines have been carried out by the spectral domain approach(SDA). The effects of variations of excited pulse width on the crosstalks of the high-speed microstrip coupled-lines are also investigated. It has been well known that the crosstalk spike level is monotonously increased when the coupling length and effective permittivity of substrate are increased. In this paper, it is found that the variations of crosstalk level are not further monotonous as shortening the exciting pulse width toward several picosecond. The results are verified by the generalized S-parameter technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.12-18
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• 2007

As an arc fault interrupter, the AFCI mentioned in this paper has been designed to detect and interrupt arc faults due to wire deterioration, insulation, wire damage, loose connection, and excessive mechanical damage. Since AFCI is digital and uses mechanical and electric stress, the length of interruption against overload and over-current is much shorter than the current bi-metal method. Therefore, the risk of electrical fires has been reduced.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.184-193
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• 2015

This paper proposes a cost-efficient and automatic method for large data acquisition from a test chip without expensive equipment to characterize random process variation in an integrated circuit. Our method requires only a test chip, a personal computer, a cheap digital-to-analog converter, a controller and multimeters, and thus large volume measurement can be performed on an office desk at low cost. To demonstrate the proposed method, we designed a test chip with a current model logic driver and an array of 128 current mirrors that mimic the random process variation of the driver's tail current mirror. Using our method, we characterized the random process variation of the driver's voltage due to the random process variation on the driver's tail current mirror from large volume measurement data. The statistical characteristics of the driver's output voltage calculated from the measured data are compared with Monte Carlo simulation. The difference between the measured and the simulated averages and standard deviations are less than 20% showing that we can easily characterize the random process variation at low cost by using our cost-efficient automatic large data acquisition method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.8-14
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• 2008

A fully CMOS-integrated carbon nanotube (CNT) sensor array is proposed. After the sensor chip is fabricated in commercial CMOS process, the CNTs network is formed on the top of the fabricated sensor chip through the room-temperature post-CMOS processes. When the resistance of the CNT is changed by the chemical reaction, the read-out circuit in the chip measures the charging time of the $R_{CNT}$-Capacitor. finally the information of measured frequency is converted to a digital code. The CMOS sensor chip was fabricated by standard 0.18um technology and the size of the $8{\times}8$ sensor array is $2mm{\times}2mn$. We have carried out an experiment detecting the biochemical material, glutamate, using this sensor chip. From the experiment the CMOS sensor chip shows the feasibility of sensor for the simultaneous detection of the various target materials.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.40-47
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• 2016

In this paper, a dual mode buck converter with an ability to change mode is proposed, which is suitable particularly for portable device. The problem of conventional mode control circuit is affected by load variation condition such as suddenly or slowly. To resolve this problem, the mode control was designed with slow clock method. Also, when change from the PFM(Pulse Frequency Modulation) mode to the PWM(Pulse Width Modulation) mode, to use the counter to detect a high load. And the user can select mode transition point in load range from 20mA to 90mA by 3 bit digital signal. The circuits are implemented by using BCDMOS 0.18um 2-polt 3-metal process. Measurement environment are input voltage 3.7V, output voltage 1.2V and load current range from 10uA to 500mA. And measurement result show that the peak efficiency is 86% and ripple voltage is less 32mV.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.