• Journal of Digital Contents Society
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• v.16 no.5
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• pp.805-813
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• 2015

Many researchers expect the compressive sensing and sparse recovery problem can overcome the limitation of conventional digital techniques. However, these new approaches require to solve the l1 norm optimization problems when it comes to signal reconstruction. In the signal reconstruction process, the transform computation by multiplication of a random matrix and a vector consumes considerable computing power. To address this issue, parallel processing is applied to the optimization problems. In particular, due to huge size of original signal, it is hard to store the random matrix directly in memory, which makes one need to design a procedural approach in handling the random matrix. This paper presents a new parallel algorithm to calculate random partial Haar wavelet transform based on Single Instruction Multiple Threads (SIMT) platform.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.309-312
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• 2001

In this paper, we proposed a system for bit stream wireless communication using audio/video infrared transceiver and implemented a circuit. The proposed transmitter system converted bit stream into analog signal format that is similar to NTSC. Then the analog signal can be transmitted by infrared spatial coupler for A/V signals. And the receiver system recover the bit stream by inverse process of transmitter.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.4
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• pp.33-40
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• 2016

Previous works for detecting arrhythmia have mostly used nonlinear method to increase classification accuracy. Most methods require accurate detection of ECG signal, higher computational cost and larger processing time. But it is difficult to analyze the ECG signal because of various noise types. Also in the healthcare system based IOT that must continuously monitor people's situation, it is necessary to process ECG signal in realtime. Therefore it is necessary to design efficient algorithm that classifies different arrhythmia in realtime and decreases computational cost by extrating minimal feature. In this paper, we propose R wave detection considering complexity and arrhythmia classification based on binary coding. For this purpose, we detected R wave through SOM and then RR interval from noise-free ECG signal through the preprocessing method. Also, we classified arrhythmia in realtime by converting threshold variability of feature to binary code. R wave detection and PVC, PAC, Normal classification is evaluated by using 39 record of MIT-BIH arrhythmia database. The achieved scores indicate the average of 99.41%, 97.18%, 94.14%, 99.83% in R wave, PVC, PAC, Normal.

• ETRI Journal
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• v.31 no.6
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• pp.717-724
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• 2009

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.7
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• pp.885-890
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• 2020

In the distance measurement system the time-to-digital conversion circuit used measures the distance using the time interval between the start signal and the stop signal. The time interval is generally converted to digital information using a counter circuit considering the response speed. Therefore, a clock signal with a high frequency is required to improve precision, and a clock signal with a high frequency is also required to measure fine distances. In this paper, a counter circuit was designed to increase the accuracy of distance measurement while using the same frequency. The circuit design was performed using a 0.18㎛ CMOS process technology, and the operation of the designed circuit was confirmed through HSPICE simulation. As a result of the simulation, it is possible to obtain an improvement of four times the precision compared to the case of using a general counter circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.671-672
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• 2011

Time to digital converter is designed. To obtain the digital signal from time information the analog delay element is used. Because the analog delay element shows more stable characteristics compared to the digital delay element in view point of process variation. The designed circuit has temperature stale characteristics when the range of operating temperature is from $-20^{\circ}C$ to $70^{\circ}C$. The circuit is simulated and confirmed by HSPICE.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.1
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• pp.11-19
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• 2013

A video-zoom driven audio-zoom algorithm is proposed to provide audio zooming effects according to the degree of video-zoom. The proposed algorithm is designed based on a super-directive beamformer operating with a 4-channel microphone array in conjunction with a soft masking process that uses the phase differences between microphones. The audio-zoom processed signal is obtained by multiplying the audio gain derived from the video-zoom level by the masked signal. The proposed algorithm is then implemented on a portable digital imaging device with a clock speed of 600 MHz after different levels of optimization, such as algorithmic level, C-code and memory optimization. As a result, the processing time of the proposed audio-zoom algorithm occupies 14.6% or less of the clock speed of the device. The performance evaluation conducted in a semi-anechoic chamber shows that the signals from the front direction can be amplified by approximately 10 dB compared to the other directions.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.35-46
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• 1999

A derotator VLSI which compensates for the frequency and phase errors of a received signal in digital communication systems was developed employing a CORDIC algorithm. The CORDIC circuit directly rotates the input signal according to the phase error information, thus is much simpler than the conventional derotator architecture which consists of a DDFS (Direct Digital Frequency Synthesizer) and a complex multiplier. Since a derotator needs only small phase error accumulation, a fast direction sequence generation method which exploits the linearity of the arctangent function in small angles is utilized in order to enhance the operating speed. The chip was designed and implemented using a $0.6\mu\textrm{m}$ triple metal CMOS process by the full custom layout method. The whole chip size is $6.8\textrm{mm}^2$ and the maximum operating frequency is 25 MHz.

• ETRI Journal
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• v.31 no.6
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• pp.732-740
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• 2009

This paper describes the implementation of a digital audio effect system-on-a-chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co-design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 ${\mu}m$ CMOS process and evaluated successfully on a real-time test board.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2004.05a
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• pp.736-741
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• 2004

In high-capacity disk drives with ever-growing track density, the allowable level of position error signal (PES) is becoming smaller and smaller. In order to achieve the high TPI disk drive, it is necessary to improve the writing accuracy during the STW(servo track writing) process through the reduction of TMR sources. Among the main contributors of the NRRO(Non-Repeatable Run-out) PES, the disk vibration and the HSA(head-stack assembly) vibration is considered to be one of the most significant factors. Also the most contributors of RRO(Repeatable Run- out) come from the contributors of NRRO which is written-in at the time of STW(servo track writing) process. In this paper, the experimental test result shows that the effect of NRRO on servo written-in RRO effectively can be reduced through a STW process under low dense medium condition such as semi-vacuum.