• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2004.04a
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• pp.269-274
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• 2004

The marine electronic system for safe navigation such as ECDIS has been contributing to increase the safety of navigation, decreasing the mariner's load of navigation. The ECDIS should be developed and approved by international standard of IMO for performance standard and IEC for type-approval method and required results. However, these standards have some ambiguities for us not to directly adopt them for real approval system, so we should analyze them for more clear meaning and prepare our own detail standard for type-approval system. The first thing to do for the goal of this research was to analyze the standard in detail and make ambiguity be cleared in our own standards, considering each test item in view of test methodology. For the result of analysis we could develop more evident and detail type-approval standard for each test item with test technology needed. Especially, we developed the colour differentiation test process of ECDIS monitor, which include the colour differentiation formula derived from CIE colour scheme. Several test items require sensor informations of navigation equipment compatible with IEC 61162. We also developed the signal simulator for general messages of IEC 61162 that must be provided. Additionally, the type-approval processes and standards for Back-up arrangement and RCDS mode were developed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• KIPS Transactions on Software and Data Engineering
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• v.7 no.2
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• pp.43-50
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• 2018

Biometric information computing is greatly influencing both a computing system and Big-data system based on the bio-information system that combines bio-signal sensors and bio-information processing. Unlike conventional data formats such as text, images, and videos, biometric information is represented by text-based values that give meaning to a bio-signal, important event moments are stored in an image format, a complex data format such as a video format is constructed for data prediction and analysis through time series analysis. Such a complex data structure may be separately requested by text, image, video format depending on characteristics of data required by individual biometric information application services, or may request complex data formats simultaneously depending on the situation. Since previous bio-information processing computing systems depend on conventional computing component, computing structure, and data processing method, they have many inefficiencies in terms of data processing performance, transmission capability, storage efficiency, and system safety. In this study, we propose an improved biosensing converged big data computing architecture to build a platform that supports biometric information processing computing effectively. The proposed architecture effectively supports data storage and transmission efficiency, computing performance, and system stability. And, it can lay the foundation for system implementation and biometric information service optimization optimized for future biometric information computing.

• Clinical and Experimental Reproductive Medicine
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• v.29 no.4
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• pp.323-335
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• 2002

Object: The present study was accomplished to obtain a gene expression profile of the luminal epithelium during embryo apposition in comparison of implantation (1M) and interimplantation (INTER) sites. Material and Method: The mouse uterine luminal epithelium from IM and INTER sites were sampled on day 4.5 (Day of vaginal plug = day 0.5) by Laser Captured Microdissection (LCM). RNA was extracted from LCM captured epithelium, amplified, labeled and hybridized to microarrays. Results from microarray hybridization were analyzed by Significance Analysis of Microarrays (SAM) method. Differential expression of some genes was confirmed by LCM followed by RT-PCR. Results: Comparison of IM and INTER sites by SAM identified 73 genes most highly ranked at IM, while 13 genes at the INTER sites, within the estimated false discovery rate (FDR) of 0.163. Among 73 genes at IM, 20 were EST/unknown function, and the remain 53 were categorized to the structural, cell cycle, gene/protein expression, immune reaction, invasion, metabolism, oxidative stress, and signal transduction. Of the 24 structural genes, 14 were related especially to extracellular matrix and tissue remodeling. Meanwhile, among 13 genes up-regulated at INTER, 8 genes were EST/unknown function, and the rest 5 were related to metabolism, signal transduction, and gene/protein expression. Among these 58 (53+5) genes with known functions, 13 genes (22.4%) were related with $Ca^{2+}$ for their function. Conclusions: Results of the present study suggest that 1) active tissue remodeling is occurring at the IM sites during embryo apposition, 2) the INTER sites are relatively quiescent than IM sites, and 3) the $Ca^{2+}$ may be a crucial for apposition. Search for human homologue of those genes expressed in the mouse luminal epithelium during apposition will help to understand the implantation process and/or implantation failure in humans.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1460-1468
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• 2000

The goal of this research is the real-time implementation of MPEG-1 Layer III audio decoder using the fixed-point digital signal processor of TMS320C6201 The main job for this work is twofold: one is to convert floating-point operation in the decoder into fixed-point operation while maintaining the high resolution, and the other is to optimize the program to make it run in real-time with memory size as small as possible. We, especially, devote much time to the descaling module in the decoder for conversion of floating-point operation into fixed-point operation with high accuracy. The inverse modified cosine transform(IMDCT) and synthesis polyphase filter bank modules are optimized in order to reduce the amount of computation and memory size. After the optimization process, in this paper, the implemented decoder uses about 26% of maximum computation capacity of TMS320C6201. The program memory, data ROM, data RAM used in the decoder are about 6.77kwords, 3.13 kwords and 9.94 kwords, respectively. Comparing the PCM output of fixed-point computation with that of floating-point computation, we achieve the signal-to-noise ratio of more than 60 dB. A real-time operation is demonstrated on the PC using the sound I/O and host communication functions in the EVM board.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1250-1259
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• 2012

In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-${\mu}m$ 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ${\mu}W$ and 0.126 mm2, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.45-52
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• 2008

We investigated the design of an RF-powered, wireless temperature sensor tag chip using $0.18-{\mu}m$ CMOS technology. The transponder generates its own power supply from small incident RF signal using Schottky diodes in voltage multiplier. Ambient temperature is measured using a new low-power temperature-to-voltage converter, and an 8-bit single-slope ADC converts the measured voltage to digital data. ASK demodulator and digital control are combined to identify unique transponder (ID) sent by base station for multi-transponder applications. The measurement of the temperature sensor tag chip showed a resolution of $0.64^{\circ}C/LSB$ in the range from $20^{\circ}C$ to $100^{\circ}C$, which is suitable for environmental temperature monitoring. The chip size is $1.1{\times}0.34mm^2$, and operates at clock frequency of 100 kHz while consuming $64{\mu}W$ power. The temperature sensor required a -11 dBm RF input power, supported a conversion rate of 12.5 k-samples/sec, and a maximum error of $0.5^{\circ}C$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Korean Journal of Digital Imaging in Medicine
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• v.16 no.2
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• pp.9-14
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• 2014

Purpose: The purpose of this study has attempted to evaluate and compare the image evaluation and exposure dose by respectively applying Filtered Back Projection(FBP), the existing test method, and Adaptive Statistical Iterative Reconstruction(ASIR) with different values of tube voltage during the Low Dose Computed Tomography(LDCT). Materials and Methods: With the image reconstruction method as basis, Chest Phantom was utilized with the FBP and ASIR set at 10%, 20% respectively, and the change of Tube Voltage (100kVp, 120kVp). For image evaluation, Back ground noise, Signal to Noise ratio(SNR) and Contrast to Noise ratio(CNR) were measured, and, for dose evaluation, CTDIvol and DLP were measured respectively. The statistical analysis was tested with SPSS(ver. 22.0), followed by ANOVA Test conducted after normality test and homogeneity test. (p<0.05). Results: In terms of image evaluation, there was no outstanding difference in Ascending Aorta(AA) SNR and Infraspinatus Muscle(IM) SNR with the different values of ASIR application(p<0.05), but a significant difference with the different amount of tube voltage(p>0.05). Also, there wasn't noticeable change in CNR with ASIR and different amount of Tube Voltage (p<0.05). However, in terms of dose evaluation, CTDIvol and DLP showed contrasting results(p<0.05). In terms of CTDIvol, the measured values with the same tube voltage of 120kVp were 2.6mGy with No-ASIR and 2.17mGy with 20%-ASIR respectively, decreased by 0.43mGy, and the values with 100kVp were 1.61mGy with No-ASIR and 1.34mGy with 20%-ASIR, decreased by 0.27mGy. In terms of DLP, the measured values with 120kVp were $103.21mGy{\cdot}cm$ with No-ASIR and $85.94mGy{\cdot}cm$ with 20%-ASIR, decreased by $17.27mGy{\cdot}cm$(about 16.7%), and the values with 100kVp were $63.84mGy{\cdot}cm$ with No-ASIR and $53.25mGy{\cdot}cm$ with 20%-ASIR, a decrease by $10.62mGy{\cdot}cm$(about 16.7%). Conclusion: At lower tube voltage, the rate of dose significantly decreased, but the negative effects on image evaluation was shown due to the increase of noise. For the future, through the result of the experiment, it is considered that the method above would be recommended for follow-up patients or those who get health checkup as long as there is no interference on the process of diagnosis due to the characteristics of Low Dose examination.