• Journal of Korea Multimedia Society
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• v.21 no.4
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• pp.450-463
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• 2018

Sound based machine fault diagnosis is the process consisting of detecting automatically the damages that affect the machines by analyzing the sounds they produce during their operating time. The collected sounds being inevitably corrupted by random disturbance, the most important part of the diagnosis consists of discovering the hidden elements inside the data that can reveal the faulty patterns. This paper presents a novel feature extraction methodology that combines various digital signal processing and pattern recognition methods for the analysis of the sounds produced by the drills. Using the Fourier analysis, the magnitude spectrum of the sounds are extracted, converted into two-dimensional vectors and uniformly normalized in such a way that they can be represented as 8-bit grayscale images. Histogram equalization is then performed over the obtained images in order to adjust their very poor contrast. The obtained contrast enhanced images will be used as the features of our diagnosis system. Finally, principal component analysis is performed over the image features for reducing their dimensions and a nonlinear classifier is adopted to produce the final response. Unlike the conventional features, the results demonstrate that the proposed feature extraction method manages to capture the hidden health patterns of the sound.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.467-472
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• 2006

This study has been done to design a precise system and develop position control algorithm to control a Composite Smoke Bomb Azimuth driving apparatus of a BLDC servo motor. Having to Blind the sight of opposite tank. the Smoke Bomb Rotational driving system needs instant response that is able to detect opponent appearance and blast the bomb at a short time. So a design that shows fast current response capability or $300[Hz]\sim500[Hz]$ is proposed. in the MIN-MAX PWM technology is used to increase the operational speed. in order to control the blasting position, a precision position control algorithm that utilizes the integral value of speed trajectory is suggested. Also these characteristics are monitored and assessed by the PC based monitoring program which shows the graphs of current, voltage, position, and speed parameters. The main controller is based on a TMS320VC33 high performance floating-point DSP(Digital Signal Process) and the PWM generator utilizes EPM7128 CPLD.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.7
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• pp.1347-1353
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• 2015

We implemented a 10 Gb/s 4-channel vertical cavity surface emission lasers (VCSEL) driver array in a $0.13{\mu}m$ CMOS process technology. To enhance high current resolution, power dissipation, and chip space area, digital APC/AMC with time division sensing technology is primarily adopted. The measured -3 dB frequency bandwidth is 9.2 GHz; the small signal gain is 10.5 dB; the current resolution is 0.01 mA/step, suitable for the wavelength operation up to 10 Gb/s over a wide temperature range. The proposed APC and AMC demonstrate 5 to 20 mA of bias current control and 5 to 20 mA of modulation current control. The whole chip consumes 371 mW of low power under the maximum modulation and bias currents. The active chip size is $3.71{\times}1.3mm^2$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.5
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• pp.29-38
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• 1985

In this paper we have designed and implemented in real time a simple, efficient and flexible AOPCM cosec using a high speed digital processor, NEC 7720. For ADPCM system, we have used an instantaneous adaptive quantizer and a first-order fixed predictor. The software for NEC 7720 has been developed and it was found that the NEC 7720 was capable of performing the entire ADPCAt algorithm for 4 channels in real time as optimizing the program. Computer simulation has born made to investigate a computational accuracr of NEC 7720 and to de-termine necessary parameters for a ADPCM codec. Real telephone speech, RC-shaped Gaussian noise and 1004 Hz tone signal were used for simulation. In simulation, the parameters werc optimized from the computed SNR and the informal listening test. The developed software was tested in real time operation using a hardware emulator for NEC 7720. It took a maximum 23.25$\mu$s to encode one sample and 113.5$\mu$s, including all the necessary 1/0 operations, to encode 4 channels. In the case of decoding process, it took 24.75$\mu$s to decode one sample and 119.5$\mu$s to decode 4 channels.

• The KIPS Transactions:PartB
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• v.9B no.2
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• pp.199-204
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• 2002

Since motion estimation and motion compensation methods remove the redundant data to employ the temporal redundancy in images, it plays an important role in digital video compression. Because of its high computational complexity, however, it is difficult to apply to high-resolution applications in real time environments. If we have information about the motion of an image block before the motion estimation, the location of a better starting point for the search of an exact motion vector can be determined to expedite the searching process. In this paper, we present an adaptive motion estimation approach bated on temporal correlations of consecutive image frames that defines the search pattern and determines the location of the initial search point adaptively. Through experiments, compared with DS(Diamond Search) algorithm, the proposed algorithm is about 0.1∼0.5(dB) better than DS in terms of PSNR(Peak Signal to Noise Ratio) and improves as high as 50% compared with DS in terms of average number of search point per motion vector estimation.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.135-143
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• 1998

Several equalizers are applied to the DVD-ROM(Digital Versatile Disc-Read Only Memory) system. Because imperfect writing process may cause nonlinear distortion in the reply signal, neural equalizers which have strong nonlinear mapping capability are applied to the system to compensate the nonlinear distortion. Experimental results to verify that the combination of decision-feedback type equalizers and modulation code is formidable are also given. The experimental results shwo that the SNR gain of the neural equalizers over the conventional equalizers becomes much as the nonlinearity in the channel increases. Furthermore, the decision-feedback type equalizers outperform the equalizers which have no decision-feedback in eliminating ISI(Intersymbol Interference) of random data sequence but there is no performance gain of the decision-feedback type equalizers over the equalizers without decision-feedback when these are applied to compensate the ISI of modulation-encoded data sequence.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1442-1447
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• 2004

In this paper, a 6-Bit CMOS Folding and Interpolating AD Converter is presented. The converter is considered to be useful as an integrated part of a VLSI circuit handling both analog and digital signals as in the case of HDD or LAN applications. A built-in analog circuit for VLSI of a high-speed data communication requires a small chip area, low power consumption, and fast data processing. The proposed folding and interpolating AD Converter uses a very small number of comparators and interpolation resistors, which is achieved by cascading a couple of folders working in different principles. This reduced number of parts is a big advantage for a built-in AD converter design. The design is based on 0.25m double-poly 2 metal n-well CMOS process. In the simulation, with the applied 2.5V and a sampling frequency of 500MHz, the measurements are as follows: power consumption of 27mw, INL and DNL of $\pm$0.1LSB, $\pm$0.15LSB each, SNDR of 42dB with an input signal of 10MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.861-862
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• 2015

In this paper we present a low area 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter). The proposed circuit is fabricated using Magnachip/SK Hynix 1-Poly 6-Metal $0.18-{\mu}m$ CMOS process, and it is powered by a 1.8-V supply. Total chip area is reduced by replacing the MIM capacitors with MOS capacitors instead of the capacitors consisting of overall part in chip area. The proposed circuit showed improved power dissipation of 1.9mW, and chip area of $0.45mm^2$ as compared to conventional research results at the power supply of 1.8V. The designed circuit also showed high SNDR (Signal-to-Noise Distortion Ratio) of 70.51dB, and excellent effective number of bits of 11.4bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3C
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• pp.296-306
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• 2003

In this paper, algorithm for non-iterative decoding method is proposed and fractal image decoder based on non-iterative fractal decoding algorithm used general purpose digital signal processors is designed and implemented. The algorithm is showed that the attractor image can be obtained analytically whe n the image is encoded using the fractal algorithm proposed by Monro and Dudbridge, in which the corresponding domain block for a range block is fifed. Using the analytical formulas, we can obtain the attractor image without iteration procedure. And we get general formulas of obtained analytical formulas. Computer simulation results for various test images show that we can increase the image decoding speed by more than five times when we use the analytical formulas compared to the previous iteration methods. The fractal image decoder contains two ADSP2181's and perform image decoding by three stage pipeline structure. The performance tests of the implemented decoder is elapsed 31.2ms/frame decoding speed for QCIF data when all the frames are decoded. The results enable us to process the real-time fractal decoding over 30 frames/sec.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.12 s.354
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• pp.61-67
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• 2006

This paper proposes the algorithm for tracking of the residual phase errors incurred by carrier frequency offset and sampling frequency offset in the orthogonal frequency division multiplexing (OFDM) systems which are suitable for high data rate wireless communications. In the OFDM systems the subcarriers which are orthogonal to each other are modulated by digital data and transmitted simultaneously. The carrier frequency offset causes degradation of signal to noise ratio(SNR) performance and interference between the adjacent subcarriers. The errors in the sampling timing caused by the sampling frequency difference between the transmitter and the receiver sides also cause a major performance degradation in the OFDM systems. The residual error tracking and compensation mechanism is essential in the OFDM system since the carrier and the sampling frequency offset cause the loss of orthogonality resulting in the system performance loss. This paper proposes the scheme where the channel gain and the payload data information are reflected in the residual error tracking process which results in the reduction of the estimation error and the tracking performance improvements under the frequency selective fading wireless channels.