• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.989-998
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• 2012

A ratio type of capacitance measurement circuit is proposed to measure an extremely small value of the fF capacitance on this paper. This measurement circuit is formed with a switched-capacitor integrator, a comparator, and logic circuit blocks to control the switches. It converts the measured ratio value between the known value of on-chip capacitor and the unknown value of capacitor to the digital signal. The fF capacitance with minimized error can be obtained by calculating this ratio. This proposed circuit is designed with standard CMOS $0.18{\mu}m$ process, and various HSpice simulations prove that this capacitance measurement circuit is able to measure the capacitance under 5fF with less than ${\pm}0.3%$ error rate.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.196-198
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• 2003

Virtually every digital signal processors(DSPs) support on-chip multi- memory banks that allow the processor to access multiple words of data from memory in a single instruction cycle. Also, all existing fixed-point DSPs have irregular architecture of heterogeneous register which contains multiple register files that are distributed and dedicated to different sets of instructions. Although there have been several studies conducted to efficiently assign data to multi-memory banks, most of them assumed processors with relatively simple, homogeneous general-purpose resisters. Therefore, several vendor-provided compilers fer DSPs were unable to efficiently assign data to multiple data memory banks. thereby often failing to generate highly optimized code fer their machines. This paper presents an algorithm that helps the compiler to efficiently assign data to multi- memory banks. Our algorithm differs from previous work in that it assigns variables to memory banks in separate, decoupled code generation phases, instead of a single, tightly-coupled phase. The experimental results have revealed that our decoupled algorithm greatly simplifies our code generation process; thus our compiler runs extremely fast, yet generates target code that is comparable In quality to the code generated by a coupled approach

• Journal of Power Electronics
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• v.13 no.3
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• pp.400-408
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• 2013

This paper presents a discrete state-space controller using state feedback control and feed-forward decoupling to provide a desirable control bandwidth and control stability for dynamic voltage restorers (DVR). The paper initially discusses three typical applications of a DVR. The load-side capacitor DVR topology is preferred because of its better filtering capability. The proposed DVR controller offers almost full controllability because of the multi-feedback of state variables, including one-beat delay feedback. Feed-forward decoupling is usually employed to prevent disturbances of the load current and source voltage. Directly obtaining the feed-forward paths of the load current and source voltage in the discrete domain is a complicated process. Fortunately, the full feed-forward decoupling strategy can be easily applied to the discrete state-space controller by means of continuous transformation. Simulation and experimental results from a digital signal processor-based system are included to support theoretical analysis.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.270-272
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• 1996

This paper describes the dissipation factor measuring techniques of insulating oil on operating pole transformer by using digital signal processor. After applying voltage to the electrodes which is installed in a transformer, acquiring source voltage and current of electrodes and using cross-correlation techniques, we can check the dissipation factor of insulating oil. To improve measuring accuracy and the speed of process, we use hardware such as TMS320C31 DSP board and software such as cross-correlation techniques and rectangular window techniques. We simulated the measuring accuracy and the degree of the noise effect of this new measuring techniques by using computer simulation, and compared the simplified measuring devices with schering bridge on degraded insulating oil. The result showed that this measuring technique can be used as diagnostic method on the pole transformers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1887-1894
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• 2010

This paper proposes a new switched-capacitor sigma-delta modulator for automotive radars. Developed modulator is used to perform high-resolution analog-to-digital conversion (ADC) of high frequency band signal in a radar system. It has supply voltage of 2.7V, and has body-effect compensated switch configuration with low voltage and low distortion. The modulator has been implemented in a $0.25{\mu}m$ double-poly and triple-metal standard CMOS process, and it has die area of $1.9{\times}1.5mm^{2}$. It showed better total harmonic distortion of 20dB than the conventional bootstrapped circuit at the supply voltage of 2.7V.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.4
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• pp.805-810
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• 2011

This paper deals with the method and algorithm used to find fault locations in gas insulated transmission line. The method uses UHF sensors and digital oscilloscope to detect discharge signals emitted to the outside through insulating spacer in the event of breakdown inside GIL. UHF sensors are the external type and installed at outside of insulating spacers of GIL. And we used wavelet signal processing to analyze the discharge signals and confirm the exact fault location findings in the GIL test line. This method can overcome demerit of TDR(Time Domain Reflectometer) method having been applied to detect fault location for conventional underground transmission lines, and Ground Fault Sensors used in conventional GIS systems. TDR method requires high level of specialty and experience in analyzing the measured signals. Ground fault sensors are installed inside GIL and can be destroyed by high transient voltage. This paper's method can simplify the fault location process and minimize the damage of sensors. In addition, this method can estimate the fault location only by the time difference when discharge signals are arrived to detecting sensors at the ends of GIL sections without reasons of breakdown. To test the performance of our method, we installed sensors at the ends of test line of GIL(84m) and sensed discharge signals occurred in GIL, energized with AC voltage generator up to 700kV.

• Journal of Information Technology Services
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• v.20 no.3
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• pp.1-12
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• 2021

Reactor Coolant Pump (RCP) is core part of nuclear power plant to provide the forced circulation of reactor coolant for the removal of core heat. Properly monitoring vibration of RCP is a key activity of a successful predictive maintenance and can lead to a decrease in failure, optimization of machine performance, and a reduction of repair and maintenance costs. Here, we developed real-time RCP Vibration Analysis System (VAS) that web based platform using NoSQL DB (Mongo DB) to handle vibration data of RCP. In this paper, we explain how to implement digital signal process of vibration data from time domain to frequency domain using Fast Fourier transform and how to design NoSQL DB structure, how to implement web service using Java spring framework, JavaScript, High-Chart. We have implement various plot according to standard of the American Society of Mechanical Engineers (ASME) and it can show on web browser based on HTML 5. This data analysis platform shows a upgraded method to real-time analyze vibration data and easily uses without specialist. Furthermore to get better precision we have plan apply to additional machine learning technology.

• Journal of Korea Society of Industrial Information Systems
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• v.15 no.3
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• pp.51-57
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• 2010

Steganography techniques can be used to hide data within digital images with little or no visible change in the perceived appearance of the image. I propose a steganalysis to detecting hidden message in sequential steganography. This paper presents adjusted technique for detecting abrupt jumps in the statistics of the stego signal during steganalysis. The repeated statistical test based on CUSUM-SPRT runs constantly until it reaches decision. In this paper, I deal with a new and improved statistic $g_t$ by computing $S^{t^*}_j$.

• Nuclear Engineering and Technology
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• v.56 no.1
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• pp.189-194
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• 2024

This paper presents a radiation-hardened-by-design preamplifier that utilizes a self-compensation technique with a charge-sensitive amplifier (CSA) and replica for total ionizing dose (TID) effects. The CSA consists of an operational amplifier (OPAMP) with a 6-bit binary weighted current source (BWCS) and feedback network. The replica circuit is utilized to compensate for the TID effects of the CSA. Two comparators can detect the operating point of the replica OPAMP and generate appropriate signals to control the switches of the BWCS. The proposed preamplifier was fabricated using a general-purpose complementary metal-oxide-silicon field effect transistor 0.18 ㎛ process and verified through a test up to 230 kGy (SiO₂) at a rate of 10.46 kGy (SiO₂)/h. The code of the BWCS control circuit varied with the total radiation dose. During the verification test, the initial value of the digital code was 39, and a final value of 30 was observed. Furthermore, the preamplifier output exhibited a maximum variation error of 2.39%, while the maximum rise-time error was 1.96%. A minimum signal-to-noise ratio of 49.64 dB was measured.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.