• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.62 no.7
• /
• pp.1020-1026
• /
• 2013

Multirate filtering process on the biological signals like Electrocardiogram (ECG) and Photoplethysmogram (PPG) can be defined as the digital signal processing algorithm in which the sampling rate varies to omit or interpolate the intermediate values between the sampled data. With this aim, we suggest a new multirate filtering algorithm by deleting the extraneous data to eliminate the unwanted degradations such as granular noise due to the usage of high sampling frequency and simultaneously to detect the fiducial features of ECG and PPG with reducing the complexity of resolving fiducial points such as R-peak, Pulse peak and Pulse Transit Time (PTT). After the experimental simulations performed, we can conclude the fact that we can detect the fiducial features of ECG and PPG signal in terms of R-peak, Pulse peak and PTT without the loss of accuracy even if we do not maintain the original sampling frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.05a
• /
• pp.877-879
• /
• 2013

Imaging device such as digital TV is being popular in a modern society based on communication technology. However, because of internal and external cause of system in the process of transmission, storage and acquisition, image is degraded by noise. Therefore, the importance of denoising technology is being increased, and a research for that is being actively made. In this paper, a weighted filter algorithm that considers different pixels of masks and estimated noise variance was proposed. in order to remove AWGN. And, PSNR(peak signal to noise ratio) was used to represent the excellence of proposed algorithm.

• Transactions of the Korean Society of Automotive Engineers
• /
• v.22 no.4
• /
• pp.89-97
• /
• 2014

As the digital control technologies in automotive industry have advanced, electronic control units(ECUs) play a key-role to improve system performance. Transmission control unit(TCU) is a shifting controller for automatic transmission of which major functions are to determine the shift and manage the shifting process considering the various sensor signal on transmission and driver's commands. As with any ECU in vehicle, TCU performs complex algorithms such as shift control, diagnostic and failsafe functions. However, firmware design analysis is hardly possible by the reverse engineering due to code protection. Transmission simulator is a hardware-in-the-loop simulator which enables TCU to work in normal mode by simulating the electrical signal of TCU interface. In this research, diagnosis and failsafe algorithm implemented on commercialized TCU is analyzed by using the transmission simulator that is developed for wheel loader construction vehicle. This paper gives various experimental results on the proportional solenoid current trajectories for different operating modes, error detection criterion and limphome mode gears for all the possible cases of clutch malfunction. The derived results for conventional TCU can be applied to the development of inherent TCU algorithms and the transmission simulator can also be utilized for the test of TCU to be developed.

• Journal of Biosystems Engineering
• /
• v.12 no.3
• /
• pp.7-16
• /
• 1987

This study was carried out to develop a microcomputer-based data acquisition and control system which was able to collect the data of engine performance test automatically and control the speed and load of the engine. The results of the study are summarized as follows: 1. The signal processing devices, which were able to measure cylinder pressure, coolant temperature, compositions of exhaust gas, fuel consumption, engine rpm and torque etc., were developed. The results of calibration showed that all of devices had high accuracy ranging from 0.3% to 0.69% respectively. 2. The PIA (peripheral interface adapter) for interfacing digital signal and PTM (programmable timer module) for displaying real time every 0.0408 sec were designed and developed. 3. An engine-speed control system using a stepping motor and driver was developed. The control system had the stability, and faster settling time than the manual control system. 4. The automatic control system of electrical dynamometer, which was able to control the speed and load of dynamometer, was developed with a SSD (shackleton system driver) and D/A converter. 5. The computer programs, which were able to collect and process the data of engine tests, were developed using both the machine language and BASIC.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.8 no.4
• /
• pp.415-425
• /
• 1997

Although FHSS has many advantages over conventional digital radio communication system, field application has been so far hampered due to its complicated synchronization. In this paper, a new FHSS system is proposed which one FH signal modulated with GMSK and one chip delayed FH signal than former are sent from transmitter, and this is recovered by matching process at a heterodyne correlator in receiver; thus eliminates synchronization as a whole. Through analysis and experiment, we assure that there is possibility in this. The exper- imental result from 915~929 MHz bandwidth with 31 chips is investigated in the environment of AWGN.

• Journal of electromagnetic engineering and science
• /
• v.14 no.4
• /
• pp.399-404
• /
• 2014

A power amplifier (PA) for a femto-cell base station should be highly efficient, linear and small. The efficiency for amplification of a high peak-to-average power ratio (PAPR) signal was improved by designing an asymmetric Doherty PA (DPA). The linearity was improved by applying third-order inter-modulation (IM3) cancellation method. A small size is achieved by designing the DPA using GaN MMIC process. The implemented 2-stage DPA delivers a power-added efficiency (PAE) of 38.6% and a gain of 33.4 dB with an average power of 34.2 dBm for a 7.2 dB PAPR 10 MHz bandwidth LTE signal at 2.14 GHz.

• Proceedings of the KIEE Conference
• /
• 2007.10a
• /
• pp.195-196
• /
• 2007

Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO, five divide-by-2 circuits and several buffers. The simulation results show that the designed circuit has a phase noise at 10kHz better than -87dBc/Hz throughout the signal band and consumes 10mA from a 1.8V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.18 no.1 s.116
• /
• pp.90-95
• /
• 2007

Chaotic OOK(On-Off Keying) modulation method can be used in LDR(Low Data Rate) UWB systems. The chaotic generator in one of the most important circuit in this system. The traditional chaotic generator circuits using analog feed back technique have low yield characteristic due to the process variation. A novel quasi-chaotic signal generator using digital PN-sequence in proposed in this paper and verified in 0.18um CMOS teleology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.795-797
• /
• 2014

Image treatment has grown in its necessity in many fields due to the development of display technology used in smart phones and tablet computers. In digital imaging technology, noise is created by many causes during the process of acquiring, transmitting and treating image data. Therefore, this paper suggests a median filter that is more competent in removing noise by taking into account the direction when restoring noisy images that have been damaged by impulse noise. In order to verify the noise removal characteristics, PSNR(peak signal to noise ratio) was used for comparison against existing methods.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
• /
• v.2
• /
• pp.385-390
• /
• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.