• Journal of Power Electronics
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• 제16권6호
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• pp.2212-2220
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• 2016

Based on the conventional PID algorithm and the adaptive PID (AD-PID) algorithm, a separate sampling adaptive PID (SSA-PID) algorithm is proposed to improve the transient response of digitally controlled DC-DC converters. The SSA-PID algorithm, which can be divided into an oversampled adaptive P (AD-P) control and an adaptive ID (AD-ID) control, adopts a higher sampling frequency for AD-P control and a conventional sampling frequency for AD-ID control. In addition, it can also adaptively adjust the PID parameters (i.e. $K_p$, $K_i$ and $K_d$) based on the system state. Simulation results show that the proposed algorithm has better line transient and load transient responses than the conventional PID and AD-PID algorithms. Compared with the conventional PID and AD-PID algorithms, the experimental results based on a FPGA indicate that the recovery time of the SSA-PID algorithm is reduced by 80% and 67% separately, and that overshoot is decreased by 33% and 12% for a 700mA load step. Moreover, the SSA-PID algorithm can achieve zero overshoot during startup.

• 컴퓨터교육학회논문지
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• 제10권4호
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• pp.17-25
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• 2007

본 논문에서는 디지털논리회로의 설계에 있어 필수적인 카르노 맵 간략화 과정을 자바 애플릿을 이용하여 웹 기반 교육용 툴로 구현하였다. 학습자들은 웹브라우저를 통해서 구현된 Java 애플릿에 접근하게 되며, 디지털 논리회로의 간략화 과정에 대해 마우스로 버튼을 클릭하거나 텍스트를 채워가면서 가상실험하게 된다. 본 논문에서 자바 애플릿을 구현하는데 사용한 간략화 알고리즘은 수정된 Quine-McCluskey 기법에 기초하였으며, 구현된 자바애플릿은 효율적인 교육보조도구로서 학습자의 학습효과를 증대시킬 수 있으리라 생각된다.

• 한국항행학회논문지
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• 제17권6호
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• pp.652-657
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• 2013

논문에서는 두 가지 혼돈맵들을 연결시킨 하나의 합성맵을 기초로 사용하는 독립된 하나의 합성상태머신을 설계하는 방법 및 그 결과를 제시하였다. 혼돈2진스트림발생기로 사용하기 위하여 혼돈합성맵에 관한 디지털회로를 설계하였다. 두 가지 혼돈함수들- 톱니함수와 비뚤어진 로지스틱 함수-로 구성되는 혼돈합성함수의 이산화 진리표를 작성하였고, 디지털회로의 수학적 모델로써 간략화 된 부울대수식들을 제시하였다. 결과로써 혼돈합성함수의 맵에 관한 디지털회로들을 제시하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.970-973
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• 2003

Abstract An idea to redce the direct-path short circuit current of the CMOS digital integrated circuit is present. The sample circuit model of the CMOS digital circuit is the CMOS current-control digital output driver circuit, which are also suitable for the low voltage supply integrated circuits as the simple digital inverter, are present in this title. The circuit consists of active MOS load as the current control source, which construct from the saturated n-channel and p-channel MOSFET and the general CMOS inverter circuits. The saturated MOSFET bias can control the output current and the frequency response of the circuit. The experimental results show that lower short circuit current control can make the lower frequency response of the circuit.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1166-1169
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• 1987

A new analog-la-digital structure. called cyclic-parallel analog-to-digital(A/D) converter, has been developed for video applications. It consists of a M-bit parallel A/D converter, a digital-to-analog(D/A) converter, a differencing amplifier with gain of $2^M$ and two sample-and-hold circuits. In this structure, the input signal is circulated around the circuits K times, thereby converted into a MK-bit digital word. The proposed converter retains speed advantages of conventional series-parallel converters, with half reduced circuit components.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.819-822
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• 1998

The high complexity of digital circuits has changed the digital circuits design mehtods from schemeatic-based to hardware description languages like VHDL, verilog that make hardware faults become more hard to detect. Thus test generation to detect hardware defects is very important part of the design. But most of the test generation methods are gate-level based. In this paper new high-level test generation method to detect stuck-at-faults on gate level is described. This test generation method is independent of synthesis results and reduce the time and efforts for test generation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.1033-1036
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• 1999

This paper proposes an efficient fault diagnosis for digital circuits using multilayer neural networks. The efficient learning algorithm is also proposed for the multilayer neural network, which is combined the steepest descent for high-speed optimization and the dynamic tunneling for global optimization. The fault-diagnosis system using the multilayer neural network of the proposed algorithm has been applied to the parity generator circuit. The simulation results shows that the proposed system is higher convergence speed and rate, in comparision with system using the backpropagation algorithm based on the gradient descent.

• 실천공학교육논문지
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• 제9권1호
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• pp.41-48
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• 2017

본 논문에서는 기초 디지털 논리 회로 실습 교육 과정을 설계하기 위해, 디지털 출력을 갖는 아두이노 프로그래밍을 통한 디지털 논리회로 제어 방법을 제안하였다. 디지털 논리회로와 아두이노 프로그래밍 실습은 국내 교육과정의 고등학교 및 대학교의 공학 계열 학과에서 필수 교육과정으로 지정하고 있다. 하지만 실제 실습에는 디지털 논리회로와 아두이노 프로그래밍이 결합된 예제가 부족하고, 디지털 논리회로를 설계하고 오실로스코프 보다 저가의 비용으로 실험할 수 있는 교육 과정이 부족하다. 이에 본 논문에서는 이 문제를 해결하는 디지털 출력 명령을 통한 아두이노 프로그래밍을 통해, 디지털 논리회로를 제어하고 실습해보는 한 학기 기간의 기초 디지털 논리 회로 실습 교육 과정을 제안하였다.

• Journal of Information Display
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• 제2권2호
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• pp.1-6
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• 2001

A $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with a new integrated 8-bit parallel-serial digital data driver was proposed and designed. For high resolution, the proposed parallel-serial digital driver used serial video data rather than parallel ones. Thus, digital circuits for driving one column line could be integrated within very small width. The parallel-serial digital data driver comprised of shift registers, latches, and serial digital-to-analog converters (DAC's). We designed a $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with integrated 8-bit parallel-serial digital data drivers by a circuit simulator which has physical-based analytical model of poly-Si TFT's. The fabricated shift register well operated at 2 MHz and $V_{DD}$=10V and the fabricated poly-Si TFT serial DAC's, which converts serial digital data to an analog signal, could convert one bit within $2.8{\mu}s$. The driver circuits for one data line occupied $8100{\times}50{\mu}m^2$ with $4{\mu}m$ design rule.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.