• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.333-339
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• 2012

Global flow of communication is a trend of high speed, digitalization, and high-capacity. Furthermore, spread spectrum method has been dominantly utilized to efficiently use the frequency which is the scarce resource. The PLL (Phase Lock Loop) which is a widely used frequency synthesizer in communication systems has few problems such as status interferences and hence, this study utilized the DDS (Direct Digital Synthesis) which is a digital device that can minimize the problems of PLL for the study on the performance evaluation of high speed frequency hopping system design. We designed a system that practices high speed frequency hopping and interprets improvement of error-rates and evaluated its performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.338-347
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• 1989

In this paper, the digital frequency synthesizer with the clock ccunting method is designed and implemented to increase the performace of the digital frequency synthesizer with pahse accumulating method which was developed before. Unlike an phase accumulating method, clock countind method is supplied a continually changeable clock frequency with PLL(Phase Locked Loop) and allocated a fixed phase step with N-ary counter. Form the experimenta results, it is confirmed that any periodic distorition phenomena are disappeared, and truncation harmonics are more reduced. But the output bandwidths are decreased in inverse proportion to the counter counting number and the circuits are somewhat complex than phase accumulating method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.176-179
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• 2000

The PLL synthesizer is used often in communication system due to several merits, such as broad bandwidth, high accuracy and stability of frequency. But it is difficult to use in current digital communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed frequency synthesizer that generate the clock frequency randomly at a high speed using the DDS technology and is applied to the pattern generator systemfor for digital image.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.443-447
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• 2001

The PLL synthesizer is used often in communication system due to several merits, such as broad bandwidth, high accuracy and stability of frequency. But it is difficult to use in torrent digital communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed frequency synthesizer that generate the clock frequency randomly at a high speed using the DDS technology and is applied to the pattern generator system for digital image.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.40-46
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• 2005

A process variation compensation method called 'regulated drain detection' is proposed. This paper also shows the how this newly invented method is applied to a typical differential PLL. The proposed RDD(regulated drain detection) and its PLL application has been designed and tested in a $0.18{\mu}m$ 1-poly 3-metal plain digital process so that its stable performance and higher yield can be proven. The implemented PLL aimed to the operation range of 80MHz - 240MHz and the total die size is only $0.18{\mu}m$ including the internal loop filter. The tracking jitter characteristics is measured to less than 150 peak-to-peak under l.8V supply rail.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.6
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• pp.489-497
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• 2001

The proposed dobule phase locked loop and active multiple interphase reactor are used to eliminate the circular current and the voltage ripples caused by the system parameter unbalance of parallel connected UPSs. In this paper, digital controller for the dobule PLL and active interphase reactor is implemented with ADSP21061 as an aspect of functional convenience.

• Proceedings of the KIEE Conference
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• 1998.07a
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• pp.25-27
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• 1998

The switched reluctance motor(SRM) drive system provides a good adjustable speed and torque characteristics. However, it also has some drawbacks such as relatively high torque ripple and acoustic noise which are caused by the torque production mechanism. To reduce torque ripple and to have precise speed control, PLL technique is adopted. The PLL system in conjunction with dynamic dwell angle control scheme has good speed regulation characteristics. Digital control system with a 80c196kc micro-controller is used to be realized this drive system. Test results show that the suggested control system has the ability of dynamic and precise speed control.

• Proceedings of the KIEE Conference
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• 2005.04a
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• pp.200-202
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• 2005

In this paper, improved rotor position estimation for position sensorless control system of the SRM (Switched Reluctance Motor) is presented. For more accurate rotor position estimation, the PLL (Phase Locked Loop) based position interpolation is adapted. In the current-flux-rotor position lookup table based rotor position estimation, the inherent current and flux-linkage ripple can cause the position estimation error. Instead of the conventional low-pass filter, the PLL based position interpolation technique is used for the better dynamic performance. The developed rotor position estimation scheme is realized using TMS320F2812 digital signal processor and prototype 1-hp SRM.