• 제목/요약/키워드: differential feedback

검색결과 183건 처리시간 0.024초

자기-바이어스 슈퍼 MOS 복합회로를 이용한 공정 검출회로 (A Process Detection Circuit using Self-biased Super MOS composit Circuit)

  • 서범수;조현묵
    • 융합신호처리학회논문지
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    • 제7권2호
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    • pp.81-86
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    • 2006
  • 본 논문에서는 새로운 개념의 공정 검출 회로를 제안하였다. 제안된 공정 검출 회로는 장채널 트랜지스터와 최소의 배선폭을 갖는 단채널 트랜지스터 사이의 공정변수의 차이를 비교한다. 이 회로는 공정 변이에 따라 발생하는 캐리어 이동도의 차이를 이용하여 이에 비례하는 차동 전류를 생성해 낸다. 이 방법에서는 고 이득 연산증폭기를 사용한 궤환 회로를 구현함으로써 두 개의 트랜지스터의 드레인 전압이 같아지도록 유지한다. 또한, 본 논문은 제안한 자기-바이어스 슈퍼 MOS 복합회로를 이용하여 고 이득 자기-바이어스 rail-to-rail 연산증폭기를 설계하는 새로운 방법을 소개한다. 설계된 연산증폭기의 이득은 단상의 $0.2V{\sim}1.6V$ 공통모드 범위에서 100dB 이상으로 측정되었다 최종적으로, 제안한 공정 검출 회로는 차동 VCO 회로에 직접 적용하였으며, 설계된 VCO 회로를 통해서 공정 검출 회로가 공정 코너들을 성공적으로 보상하고 광범위한 동작 영역에서 안정된 동작을 수행함을 확인할 수 있었다.

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Fully Differential 5-GHz LC-Tank VCOs with Improved Phase Noise and Wide Tuning Range

  • Lee, Ja-Yol;Park, Chan-Woo;Lee, Sang-Heung;Kang, Jin-Young;Oh, Seung-Hyeub
    • ETRI Journal
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    • 제27권5호
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    • pp.473-483
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    • 2005
  • In this paper, we propose two LC voltage-controlled oscillators (VCOs) that improve both phase noise and tuning range. With both 1/f induced low-frequency noise and low-frequency thermal noise around DC or around harmonics suppressed significantly by the employment of a current-current negative feedback (CCNF) loop, the phase noise in the CCNF LC VCO has been improved by about 10 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise of the CCNF VCO was measured as -112 dBc/Hz at 6 MHz offset from 5.5 GHz carrier frequency. Also, we present a bandwidth-enhanced LC VCO whose tuning range has been increased about 250 % by connecting the varactor to the bases of the cross-coupled pair. The phase noise of the bandwidth-enhanced LC-tank VCO has been improved by about 6 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise reduction has been achieved because the DC-decoupling capacitor Cc prevents the output common-mode level from modulating the varactor bias point, and the signal power increases in the LC-tank resonator. The bandwidth-enhanced LC VCO represents a 12 % bandwidth and phase noise of -108 dBc/Hz at 6 MHz offset.

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차량 요레이트 피드백을 통한 가상 제동 압력 센서 개발 (Virtual Brake Pressure Sensor Using Vehicle Yaw Rate Feedback)

  • 유승한
    • 대한기계학회논문집A
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    • 제40권1호
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    • pp.113-120
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    • 2016
  • 본 연구에서는 좌/우 편제동을 통해 차량의 요 모션을 제어하는 제동 기반 요모멘트 제어 시스템에서의 가상 제동 압력 센서를 개발하였다. 제동 압력을 추정하기 위해 유압시스템을 경험적 방법으로 모델링하였고 이를 기반으로 요레이트 피드백 제동 압력 관측기를 설계하였다. 차량 요레이트 동역학에 존재하는 외란의 영향을 최소화 하기 위해 외란 적응 기법, 외란 축소 기법 및 최적 이득 기법을 관측기 설계에 적용하였고 그 방법들 간의 성능 비교 및 검증을 HILS 를 통해 수행하였다. 그 결과 외란 축소 방식의 견실 관측기의 압력 추정 성능이 일반적인 Luenberger 관측기 대비 가장 우수하였으며 그 원인에 대해 분석하였다.

Low-Voltage Tunable Pseudo-Differential Transconductor with High Linearity

  • Galan, Juan Antonio Gomez;Carrasco, Manuel Pedro;Pennisi, Melita;Martin, Antonio Lopez;Carvajal, Ramon Gonzalez;Ramirez-Angulo, Jaime
    • ETRI Journal
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    • 제31권5호
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    • pp.576-584
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    • 2009
  • A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 ${\mu}m$ CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 ${\mu}A/V$ to 165 ${\mu}A/V$) and a total harmonic distortion of -67 dB at 1 MHz for an input of 1 Vpp and a supply voltage of 1.8 V.

저주파 잡음이 억압된 5.5 GHz 전압제어발진기 (A 5.5 GHz VCO with Low-Frequency Noise Suppression)

  • 이자열;배현철;이상흥;강진영;김보우;오승엽
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.465-468
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    • 2004
  • In this paper, we describe the design and implementation of the new current-current negative feedback (CCNF) voltage-controlled oscillator (VCO), which suppresses 1/f induced low-frequency noise. By means of the CCNF, the high-frequency noise as well as the low-frequency noise is prevented from being converted into phase noise. The proposed CCNF VCO shows 11-dB reduction in phase noise at 10 kHz offset, compared with the conventional differential VCO. The phase noise of the proposed VCO is -87 dBc/Hz at 10 kHz offset frequency from 5.5-GHz carrier. The proposed VCO consumes 14.0 mA at 2.0 V supply voltage, and shows single-ended output power of -12.0 dBm.

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A Low Phase Noise 5.5-GHz SiGe VCO Having 10% Bandwidth

  • Lee Ja-Yol;Park Chan Woo;Bae Hyun-Cheol;Kang Jin-Young;Kim Bo-Woo;Oh Seung-Hyeub
    • Journal of electromagnetic engineering and science
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    • 제4권4호
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    • pp.168-174
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    • 2004
  • A bandwidth-enhanced and phase noise-improved differential LC-tank VCO is proposed in this paper. By connecting the varactors to the bases of the cross-coupled transistors of the proposed LC-tank VCO, its input negative resistance has been widened. Also, the feedback capacitor Cc in the cross-coupling path of the proposed LC-tank VCO attenuates the output common-mode level modulated by the low-frequency noise because the modulated common-mode level jitters the varactor bias point and degrades phase noise. Compared with the fabricated conventional LC-tank VCO, the proposed LC-tank VCO demonstrates $200\;\%$ enhancement in tuning range, and 6 - dB improvement in phase noise at 6 MHz offset frequency from 5.4-GHz carrier. We achieved the phase noise of - 106 dBc/Hz at 6 MHz offset, and $10\;\%$ tuning range from the proposed LC-tank VCO. The proposed LC-tank VCO consumes 12 mA at 2.5 V supply voltage.

High-speed CMOS Frequency Divider with Inductive Peaking Technique

  • Park, Jung-Woong;Ahn, Se-Hyuk;Jeong, Hye-Im;Kim, Nam-Soo
    • Transactions on Electrical and Electronic Materials
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    • 제15권6호
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    • pp.309-314
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    • 2014
  • This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with $0.18-{\mu}m$ CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.

확장영역 전기자동차 응용을 위한 유도전동기의 고효율 운전 특성 (The High Efficiency Operating Characteristics of the Induction Motor for Extended Range Electric Vehicle Applications)

  • 유두영;손진근;전희종;최욱돈
    • 전기학회논문지P
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    • 제65권4호
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    • pp.273-279
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    • 2016
  • In this paper, a high-performance control of the induction motor for electric car was implemented to escape dependence of the rare earth magnet. Proposed high-efficiency control algorithm is a Direct Rotor Field-Oriented Control method that is insensitive to the fluctuation of motor parameters. In the DRFOC method, we need to compensate fluctuation of stator transient inductance and magnetizing inductance caused by the magnetic saturation of induction motor in high-speed area. This paper proposes Back-EMF Observer based on stator current estimator of Luenberger style. Motor control system applied the Voltage Feedback Flux Weakening Control method for high-speed operation. The proposed algorithm was verified through tests by the power train of Extended Range Electric Vehicle consists of induction motor and differential gear.

Design of nonlinear optimal regulators using lower dimensional riemannian geometric models

  • Izawa, Yoshiaki;Hakomori, Kyojiro
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1994년도 Proceedings of the Korea Automatic Control Conference, 9th (KACC) ; Taejeon, Korea; 17-20 Oct. 1994
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    • pp.628-633
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    • 1994
  • A new Riemannian geometric model for the controlled plant is proposed by imbedding the control vector space in the state space, so as to reduce the dimension of the model. This geometric model is derived by replacing the orthogonal straight coordinate axes on the state space of a linear system with the curvilinear coordinate axes. Therefore the integral manifold of the geometric model becomes homeomorphic to that of fictitious linear system. For the lower dimensional Riemannian geometric model, a nonlinear optimal regulator with a quadratic form performance index which contains the Riemannian metric tensor is designed. Since the integral manifold of the nonlinear regulator is determined to be homeomorphic to that of the linear regulator, it is expected that the basic properties of the linear regulator such as feedback structure, stability and robustness are to be reflected in those of the nonlinear regulator. To apply the above regulator theory to a real nonlinear plant, it is discussed how to distort the curvilinear coordinate axes on which a nonlinear plant behaves as a linear system. Consequently, a partial differential equation with respect to the homeomorphism is derived. Finally, the computational algorithm for the nonlinear optimal regulator is discussed and a numerical example is shown.

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이중-적분을 이용한 용량형 센서용 스위치드-캐패시터 인터페이스 (A Switched-Capacitor Interface Based on Dual-Slope Integration)

  • 정원섭;차형우;류승용
    • 대한전자공학회논문지
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    • 제26권11호
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    • pp.1666-1671
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    • 1989
  • A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.

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