• Title/Summary/Keyword: dielectric breakdown

Search Result 649, Processing Time 0.025 seconds

Fabrication of Organic Thin-Film Transistor Using Vapor Deposition Polymerization Method (Vapor Deposition Polymerization 방법을 이용한 유기 박막 트렌지스터의 제작)

  • 표상우;김준호;김정수;심재훈;김영관
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2002.07a
    • /
    • pp.190-193
    • /
    • 2002
  • The processing technology of organic thin-film transistors (Ons) performances have improved fur the last decade. Gate insulator layer has generally used inorganic layer, such as silicon oxide which has properties of a low electrical conductivity and a high breakdown field. However, inorganic insulating layers, which are formed at high temperature, may affect other layers termed on a substrate through preceding processes. On the other hand, organic insulating layers, which are formed at low temperature, dose not affect pre-process. Known wet-processing methods for fabricating organic insulating layers include a spin coating, dipping and Langmuir-Blodgett film processes. In this paper, we propose the new dry-processing method of organic gate dielectric film in field-effect transistors. Vapor deposition polymerization (VDP) that is mainly used to the conducting polymers is introduced to form the gate dielectric. This method is appropriate to mass production in various end-user applications, for example, flat panel displays, because it has the advantages of shadow mask patterning and in-situ dry process with flexible low-cost large area displays. Also we fabricated four by four active pixels with all-organic thin-film transistors and phosphorescent organic light emitting devices.

  • PDF

Evaluation Method I of the Small Current Breaking Performance for SF(sub)6-Blown High-Voltage Gas Circuit Breakers (초고압 $SF_6$ 가스차단기의 소전류 차단성능 해석기술 I)

  • 송기동;이병운;박경엽;박정후
    • The Transactions of the Korean Institute of Electrical Engineers B
    • /
    • v.50 no.7
    • /
    • pp.331-337
    • /
    • 2001
  • With the increasing reliability of analysis schemes and the dramatically increased calculating speed, the computer simulation has become and indispensable process to predict the interruption capacity of circuit breakers. Generally, circuit breakers have to possess both the small current and large current interruption abilities and the circuit breaker designers need to evaluate its capacities to save the time and the expense. The analysis of small current and the large current interruption performances have been considered separately because the phenomena occurring in a interrupter are quite different. To analyze the dielectric recovery after large current interruption many physical phenomena such as heat transfer, convection and arc radiation, the nozzle ablation, the ionization of high temperature SF(sub)6 gas, the electric and themagnetic forces and so forth mush be considered. However, in the analysis of small current interruption performance only the cold gas flow analysis needs to be carried out because the capacitive current is to small that the influence from the current can be neglected. In this paper, an empirical equation which is obtained from a series of tests to estimate the dielectric recovery strength has been applied to a real circuit breaker. The results of analysis have been compared with the test results and the reliability has been investigated.

  • PDF

Effects of Bottom Electrode to Dielectric and Electrical Properties of MOD Derived Ferroelectric SBT Thin Films (MOD 법으로 제조한 강유전성 SBT 박막에서 하부전극이 유전 및 전기적 특성에 미치는 영향)

  • 김태훈;송석표;김병호
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.13 no.8
    • /
    • pp.694-699
    • /
    • 2000
  • S $r_{0.9}$/B $i_{2.1}$/T $a_{2}$/ $O_{9}$ solutions was synthesized by MOD (metalorganic decomposition) method. SBT thin films with 2000$\AA$ thickness were prepared on Ir $O_2$/ $SiO_2$/Si and Pt/Ti/ $SiO_2$/Si substrates using the spin coating process and then investigated the dielectric and electrical properties of them. In the case of using Ir $O_2$bottom electrode the hysteresis loop was saturated at lower temperature than Pt/Ti electrode but the breakdown phenomenon was occurred at low voltage because of the rough surface morphology and porous microstructure of SBT thin films. As the results of the fatigue and imprint characteristics related to the lifetime and reliability of devices after 10$^{10}$ cycles the fatigue rates were about 10% at the Ir $O_2$and Pt/Ti bottom electrodes. Both SBT thin films with Ir $O_2$ and with Pt/Ti bottom electrodes show a slight tendency to imprint after 10$^{9}$ cycles but do not lead to a failure.e.e.

  • PDF

Microstructure and Varistor Properties of ZVMND Ceramics with Sintering Temperature

  • Nahm, Choon-Woo
    • Transactions on Electrical and Electronic Materials
    • /
    • v.16 no.4
    • /
    • pp.221-225
    • /
    • 2015
  • The sintering effect on the microstructure, electrical properties, and dielectric characteristics of ZnO-V2O5-MnO2-Nb2O5-Dy2O3-based ceramics was investigated. With the increase of sintering temperature from 875 to 950℃, the density of the sintered pellets decreased from 5.57 to 5.45 g/cm3 and the average grain size increased from 4.3 to 10.9 μm. The breakdown field decreased noticeably from 6,095 to 996 V/cm with the increase of sintering temperature. The varistor ceramics sintered at 900℃ exhibited the best nonlinear properties: 39.2 in the nonlinear coefficient and 0.24 mA/cm2 in the leakage current density. The dielectric constant increased sharply from 658.6 to 2,928.8 with the increase of sintering temperature. On the whole, the dissipation factor exhibited a fluctuation with the increase of the sintering temperature, and a minimum value of 0.284 at 900℃.

Reliability of N/O($SiO_2$/$Si_3$$N_4$) Films According to Top Oxidation Condition (상부산화 조건에 따른 N/O($SiO_2$/$Si_3$$N_4$) 구조막의 신뢰성 평가)

  • 구경완;홍봉식
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.29A no.9
    • /
    • pp.20-28
    • /
    • 1992
  • Dielectric thin film of N/O ($Si_{3]N_{4}/SiO_{2}$) for high density stacked dynamic-RAM cell was formed by LPCVD and oxidation(dry & pyrogenic oxidation methods) of the top 7nm $Si_{3]N_{4}$ film. The thickness, structure and composition of this film were measured by ellipsometer, high resolution TEM, AES and SIMS. The insulating characteristics(I-V characteristics) were investigated by HP 4145, and the characteristics of TDDB (Time Dependent Dielectric Breakdown) were evaluated by using CCST(Current Constant Stress Time) method. In this experiment, The optimum oxidation condition for preparation of good insulating and TDDB characteristics of N/O film was pyrogenic oxidation at 85$0^{\circ}C$ for 30 minutes. The leakage current was reduced from 400pA to 7.5pA when SiO$_{2}$ film with thickness of 2nm was formed on the top of $Si_{3]N_{4}$ film by the pyrogenic oxidation method.

  • PDF

Fabrication and Properties of GaAs-MIS Capacitor using $SF_6$ Plasma Discharge ($SF_6$ 플라즈마 방전을 이용한 G3AS-MIS 커패시터의 제작 밑 특성)

  • 이남열;정순원;김광호;유병곤;이원재;유인규;양일석
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 1999.11a
    • /
    • pp.29-32
    • /
    • 1999
  • $GaF_3$ films were directly grown on p' and p-type GaAs(100) substrates using a $SF_6$ plasma discharge system. GaAs MIS(Meta1-Insulator-Semiconductor) capacitor was successfully fabricated for about 1 hour at temperature $290^{\circ}C$ using the as-grown $GaF_3$ films. The as-grown films on p'-GaAs exhibited a current density of less than 6.68 $\times$ $1O^{-9}$ A/$cm^2$ at a breakdown field of 500kV/cm and a refractive index of 2.0 ~ 2.3 at a wavelength of 632.8 nm. The dielectric constant was about 5 derived from 1 MHz capacitance-voltage (C-V) measurements. Dielectric dispersion of the fluoridated films on p'-GaAs measured ranged from 100 Hz to 10 MHz was not observed.

  • PDF

Microstructure and Electrical Properties of $SiO_2$-Doped Zinc Oxide Varistors ($SiO_2$가 첨가된 산화아연 바리스터의 미세구조 및 전기적 특성)

  • 남춘우;정순철
    • Electrical & Electronic Materials
    • /
    • v.10 no.7
    • /
    • pp.659-667
    • /
    • 1997
  • The influence of SiO$_2$on the microstructure and electrical properties of zinc oxide varistor was investigated. Zn$_2$SiO$_4$third phase in the sintered body was found at grain boundaries, multiple grain junctions, and occasionally within ZnO grains. This phase acted as a grain growth inhibitor, which retard the grain growth of the ZnO matrix by impeding migration on the grain boundaries. As SiO$_2$ addition increases, average grain size decreased from 40.6${\mu}{\textrm}{m}$ to 26.9${\mu}{\textrm}{m}$ due to the pinning effect by Zn$_2$SiO$_4$ and drag effect by Si segregation at grain boundaries, the breakdown voltage consequently increased. When SiO$_2$ addition is increased, interface state density decreased, however, the barrier height increased by decrease of donor concentration, as a result, the nonlinear exponent increased and leakage current decreased. While, as SiO$_2$ addition increase, it was found that the apparent dielectric loss factor shows a tendency of decrease. Wholly, electrical properties of zinc oxide varistor can be said to be improved by SiO$_2$addition.

  • PDF

Improvement of Gate Dielectric Characteristics in MOS Capacitor by Deuterium-ion Implantation Process (중수소 이온 주입에 의한 MOS 커패시터의 게이트 산화막 절연 특성 개선)

  • Seo, Young-Ho;Do, Seung-Woo;Lee, Yong-Hyun;Lee, Jae-Sung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.24 no.8
    • /
    • pp.609-615
    • /
    • 2011
  • This paper is studied for the improvement of the characteristics of gate oxide with 3-nm-thick gate oxide by deuterium ion implantation methode. Deuterium ions were implanted to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas to nitrogen was performed to remove the damage of D-implantation. We simulated the deuterium ion implantation to find the optimum condition by SRIM (stopping and range of ions in matter) tool. We got the optimum condition by the results of simulation. We compare the electrical characteristics of the optimum condition with others terms. We also analyzed the electrical characteristics to change the annealing conditions after deuterium ion implantation. The results of the analysis, the breakdown time of the gate oxide was prolonged in the optimum condition. And a variety of annealing, we realized the dielectric property that annealing is good at longer time. However, the high temperature is bad because of thermal stress.

Design and Analysis of Electrical Properties of a Multilayer Ceramic Capacitor Module for DC-Link of Hybrid Electric Vehicles

  • Yoon, Jung-Rag;Moon, Bong Hwa;Lee, Heun Young;Jeong, Dae Yong;Rhie, Dong Hee
    • Journal of Electrical Engineering and Technology
    • /
    • v.8 no.4
    • /
    • pp.808-812
    • /
    • 2013
  • Multilayer capacitors with high ripple current and high capacitance were manufactured. The electrical properties of these capacitors were characterized for potential application for DC-link capacitors in hybrid electric vehicle inverters. Internal electrode structures were designed to achieve high capacitance and reliability. A single multilayer capacitor showed $0.46{\mu}F/cm^3$ of capacitance, 0.65% of dielectric loss, and 1450 V to 1650 V of dielectric breakdown voltage depending on the design of the internal electrode. The capacitor module designed with several multilayer capacitors gave a total capacitance of $450{\mu}F$, which is enough for hybrid electric vehicles. In particular, an equivalent series resistance of $4.5m{\Omega}$ or less will result in 60 $A_{rms}$, thereby reaching the allowed ripple current for hybrid electric vehicles.

Surge Characteristics Analysis of Three-phase Virtual Chopping at Vacuum Circuit Breaker (진공차단기 3상 동시 차단시의 서지 특성 분석)

  • Kim, Jong-Gyeum
    • The Transactions of The Korean Institute of Electrical Engineers
    • /
    • v.67 no.9
    • /
    • pp.1159-1164
    • /
    • 2018
  • Vacuum circuit breakers(VCB) are widely used for current interruption of high-voltage inductive loads such as induction motors. This VCB can be chopped off before the current zero due to its high arc-extinguishing capability. One of the outstanding features of VCB is that it can cut off high frequency re-ignition current more than other circuit breakers. If the transient recovery voltage generated in the arc extinguishing is higher than the dielectric strength of the circuit breaker, a re-ignition phenomenon occurs. The surge voltage of the re-ignition is very high in magnitude and the steepness of the waveform is so severe that it can act as a high electrical stress on the winding. If the high frequency current of one phase affects the other two phases when the re-ignition occurs, it may cause a high surge voltage due to the virtual current chopping. If the magnitude of the voltage allowed in the motor winding is high or the waveform level is too severe, it may lead to insulation breakdown. Therefore, it is necessary to reduce the voltage to within a certain range. In this study, we briefly explain the various phenomena at the time of interruption, analyzed the magnitude of the dielectric strength and the transient recovery voltage at the simultaneous three-phase interruption that can give the greatest influence to the inductive load, proposed a method to reduce the impact.