• Title/Summary/Keyword: dielectric breakdown

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Development of Heterojunction Electric Shock Protector Device by Co-firing (동시소성형 감전소자의 개발)

  • Lee, Jung-soo;Oh, Sung-yeop;Ryu, Jae-su;Yoo, Jun-seo
    • Korean Journal of Materials Research
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    • v.29 no.2
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    • pp.106-115
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    • 2019
  • Recently, metal cases are widely used in smart phones for their luxurious color and texture. However, when a metal case is used, electric shock may occur during charging. Chip capacitors of various values are used to prevent the electric shock. However, chip capacitors are vulnerable to electrostatic discharge(ESD) generated by the human body, which often causes insulation breakdown during use. This breakdown can be eliminated with a high-voltage chip varistor over 340V, but when the varistor voltage is high, the capacitance is limited to about 2pF. If a chip capacitor with a high dielectric constant and a chip varistor with a high voltage can be combined, it is possible to obtain a new device capable of coping with electric shock and ESD with various capacitive values. Usually, varistors and capacitors differ in composition, which causes different shrinkage during co-firing, and therefore camber, internal crack, delamination and separation may occur after sintering. In addition, varistor characteristics may not be realized due to the diffusion of unwanted elements into the varistor during firing. Various elements are added to control shrinkage. In addition, a buffer layer is inserted in the middle of the varistor-capacitor junction to prevent diffusion during firing, thereby developing a co-fired product with desirable characteristics.

Study on the Performance Verification Method and Failure Mechanism of Grading Capacitor of a Two-break Circuit-breaker (2점절 차단기 균압용 콘덴서 절연파괴 고장 메커니즘 및 성능검증 방법에 관한 연구)

  • Oh, SeungRyle;Han, Kisun;Kim, TaeKyun
    • KEPCO Journal on Electric Power and Energy
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    • v.5 no.1
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    • pp.11-15
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    • 2019
  • Recently, the circuit-breaker rated voltage is getting higher as the transmission voltage increases. To increase the circuit-breaker rated voltage, a multi-break circuit-breaker which has two or more breakers in series is adopted. For multi-break circuit-breaker, a grading capacitor is used to mitigate the Transient Recovery Voltage(TRV) and control the voltage distribution across the individual interrupter units. However, all over the world, there are many failures such as mechanical damage, explosion due to insulation breakdown. Therefore, it is necessary to study the causes of failure and the new performance verification method. In this paper, we investigate the causes of dielectric breakdown of the grading capacitors in the KEPCO power system and propose the performance verification method.

Characterization of Gate Oxides with a Chlorine Incorporated $SiO_2/Si$ Interface (염소(Chlorine)가 도입된 $SiO_2/Si$ 계면을 가지는 게이트 산화막의 특성 분석)

  • Yu, Byoung-Gon;Lyu, Jong-Son;Roh, Tae-Moon;Nam, Kee-Soo
    • Journal of the Korean Vacuum Society
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    • v.2 no.2
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    • pp.188-198
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    • 1993
  • We have developed a technique for growing thin oxides (6~10 nm) by the Last step TCA method. N-channel metal-oxide-semiconductor (n-MOS) capacitor and n-channel metal-oxide-semiconductor field-effect transistor's (MOSFET's) having a gate oxide with chlorine incorporated $SiO_2/Si$ interface have been analyzed by electrical measurements and physical methods, such as secondary ion mass spectrometry (SIMS) and electron spectroscopy for chemical analysis (ESCA). The gate oxide grown with the Last strp TCA method has good characteristics as follows: the electron mobility of the MOSFET's with the Last step TCA method was increased by about 7% and the defect density at the $SiO_2/Si$ interface decreases slightly compared with that with No TCA method. In reliability estimation, the breakdown field was 18 MV/cm, 0.6 MV/cm higher than that of the gate oxide with No TCA method, and the lifetime estimated by TDDB measurement was longer than 20 years. The device lifetime estimated from hot-carrier reliability was proven to be enhanced. As the results, the gate oxide having a $SiO_2/Si$ interface incorporated with chlorine has good characteristics. Our new technique of Last step TCA method may be used to improve the endurance and retention of MOSFET's and to alleviate the degradation of thin oxides in short-channel MOS devices.

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Basic Insulation Characteristics of Conduction-Cooled HTS SMES System (전도냉각 고온초전도 SMES 시스템의 기초절연 특성)

  • Choi Jae-Hyeong;Kwang Dong-Soon;Cheon Hyeon-Gweon;Kim Sang-Hyun
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.55 no.8
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    • pp.404-410
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    • 2006
  • Toward the practical applications, on operation of conduction-cooled HTS SMES at temperatures well below 40[K] should be investigated, in order to take advantage of a greater critical current density of HTS and considerably reduce the size and weight of the system. In order to take advantage of a greater critical current density of high temperature superconducting (HTS) and considerably reduce the size and weight of the system, conduction-cooled HTS superconducting magnetic energy storage (SMES) at temperatures well below 40[K] should be investigated. This work focuses on the breakdown and flashover phenomenology of dielectrics exposed in air and/or vacuum for temperatures ranging from room temperature to cryogenic temperature. Firstly, we summarize the insulation factors of the magnet for the conduction cooled HTS SMES. And Secondly a surface flashover as well as volume breakdown in air and/or vacuum with two kind insulators has been investigated. Finally, we will discuss applications for the HTS SMES including aging studies on model coils exposed in vacuum at cryogenic temperature. The commercial application of many conduction-cooled HTS magnets, however, requires refrigeration at temperatures below 40[K], in order to take advantage of a greater critical current density of HTS and reduce considerably the size and weight of the system. The magnet is driven in vacuum condition. The need to reduce the size and weight of the system has led to the consideration of the vacuum as insulating media. We are studying on the insulation factors of the magnet for HTS SMES. And we experiment the spacer configure effect in the dielectric flashover characteristics. From the results, we confirm that our research established basic information in the insulation design of the magnet.

Formation of ultra-thin $Ta_{2}O_{5}$ film on thermal silicon nitrides (열적 성장된 실리콘 질화막위에 산화 탄탈륨 초박막의 형성)

  • 이재성;류창명;강신원;이정희;이용현
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.11
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    • pp.35-43
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    • 1995
  • To obtain high quality of $Ta_{2}O_{5}$ film, two dielectric layers of $Si_{3}N_{4}$ and $Ta_{2}O_{5}$ were subsequently formed on Si wafer. Silicon nitride films were thermally grown in 10 Torr ammonia ambient by R.F induced heating system. The thickness of thermally grown $Si_{3}N_{4}$ film was able to be controlled in the range of tens $\AA$ due to the self-limited growth property. $Ta_{2}O_{5}$ film of 200$\AA$ thickness was then deposited on the as-grown $Si_{3}N_{4}$ film about 25$\AA$ thickness by sputtering method and annealed at $900^{\circ}C$in $O_{2}$ ambient for 1hr. Stoichiometry film was prepared by the annealing in oxygen ambient. Despite the high temperature anneal process, silicon oxide layer was not grown at the interface of the layered films because of the oxidation barrier effect of Si$_{3}$N$_{4}$ film. The fabricated $Ta_{2}O_{5}$/$Si_{3}N_{4}$ film showed low leakage current less than several nA and high dielectric breakdown strength.

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Ultra low temperature polycrystalline silicon thin film transistor using sequential lateral solidification and atomic layer deposition techniques

  • Lee, J.H.;Kim, Y.H.;Sohn, C.Y.;Lim, J.W.;Chung, C.H.;Park, D.J.;Kim, D.W.;Song, Y.H.;Yun, S.J.;Kang, K.Y.
    • 한국정보디스플레이학회:학술대회논문집
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    • 2004.08a
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    • pp.305-308
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    • 2004
  • We present a novel process for the ultra low temperature (<150$^{\circ}C$) polycrystalline silicon (ULTPS) TFT for the flexible display applications on the plastic substrate. The sequential lateral solidification (SLS) was used for the crystallization of the amorphous silicon film deposited by rf magnetron sputtering, resulting in high mobility polycrystalline silicon (poly-Si) film. The gate dielectric was composed of thin $SiO_2$ formed by plasma oxidation and $Al_2O_3$ deposited by plasma enhanced atomic layer deposition. The breakdown field of gate dielectric on poly-Si film showed above 6.3 MV/cm. Laser activation reduced the source/drain resistance below 200 ${\Omega}$/ㅁ for n layer and 400 ${\Omega}$/ㅁ for p layer. The fabricated ULTPS TFT shows excellent performance with mobilities of 114 $cm^2$/Vs (nMOS) and 42 $cm^2$/Vs (pMOS), on/off current ratios of 4.20${\times}10^6$ (nMOS) and 5.7${\times}10^5$ (PMOS).

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A Review on Nanocomposite Based Electrical Insulations

  • Paramane, Ashish S.;Kumar, K. Sathish
    • Transactions on Electrical and Electronic Materials
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    • v.17 no.5
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    • pp.239-251
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    • 2016
  • The potential of nanocomposites have been drawing the intention of the researchers from energy storage to electrical insulation applications. Nanocomposites are known to improve dielectric properties, such as the increase in dielectric breakdown strength, suppressing the partial discharge (PD) as well as space charge, and prolonging the treeing, etc. In this review, different theories have been established to explain the reactions at the interaction zone of polymer matrix and nanofiller; the characterization methods of nanocomposites are also presented. Furthermore, the remarkable findings in the fields of epoxy, cross-linked polyethylene (XLPE), polypropylene and polyvinyl chloride (PVC) nanocomposites are reviewed. In this study, it was observed that there is lack of comparison between results of lab scale specimens and actual field aged cables. Also, non-standardization of the preparation methods and processing parameters lead to changes in the polymer structure and its surface degradation. However, on the positive side, recent attempt of 250 kV XLPE nanocomposite HVDC cables in service may deliver a promising performance in the coming years. Moreover, materials such as self-healing polymer nanocomposites may emerge as substitutes to traditional insulations.

Analysis of Diagnosis and Very Low Frequency Experiment to Detect of Fault on 22.9kV Class Cable (22.9kV급 케이블 결함 검출을 위한 초저주파 실험 및 현장 진단 분석)

  • Kim, Young-Seok;Kim, Taek-Hee;Kim, Chong-Min;Shong, Kil-Mok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.10
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    • pp.1780-1785
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    • 2016
  • This paper presents few case studies of state diagnosis of XLPE cables using very low frequency techniques. The power cables of 22.9kV which have installation fault were assessed using VLF technique in addition to other techniques like insulation resistance and DC voltage withstand test. From the experimental results, The dielectric loss($tan{\delta}$) values of degradation of the cable(joint, knife, needle) at $U_0$ were 5.839, 5.526 and 6.251, respectively and all values were "further study advised". VLF PD measurement was also found defective portion. These method was effective in defect to fault in the degradation of the cable. However, the breakdown did not occur in the degradation of the cable because of properties of XLPE insulation. Few case studies of using VLF $tan{\delta}$ diagnosis for fault are measured and analyzed. The $tan{\delta}$ values at $U_0$ were "further study advised" or "action required".

Accelerated Thermal Aging Measurement and Analysis of CSPE Cable for Condition Monitoring (CSPE 케이블의 상태감시를 위한 가속열화 측정 분석)

  • Park, Joung-Ho;Cha, Wang-Cheol;Lee, Jung-Hoon;Cho, Uk-Rae;Kim, Jae-Chul
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.29 no.3
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    • pp.88-95
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    • 2015
  • The accelerated thermal aging of CSPE(Chloro Sulfonate Polyethylene) was carried out for 40.41, 121.22, 202.04 days, 16.82, 50.45, 84.09 days and 7.32, 21.96, 36.59 days at 100, 110, and $120^{\circ}C$, respectively, which are equivalent to 20, 60, 100 years of aging at $50^{\circ}C$. The permittivities and the apparent densities of the accelerated thermally aged CSPE samples are increased with accelerated thermal aging year but EAB(Elongation at Break) is decreased with that. The dielectric strength and the electric breakdown of the non-accelerated and accelerated thermally aged CSPE samples do not depend on accelerated thermal aging year and applied voltage rising time. density and EAB measures.

Dielectric and Passivation-Related Properties of Pecvd PSG (PECVD PSG의 유전 및 보호막특성에 관한 연구)

  • 유현규;강영일
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.22 no.2
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    • pp.90-96
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    • 1985
  • The properties of plasma-enhanced CVD phosphorous silicate glass (PECVD PSG) for passivation layer are studied . Phosphorous contentration was analyzed with X-ray fluores-cence. As a result, PECVD PSG has a limiting phosphors concentration of about 8 mole%. Curves relating to etcll rate, infrared absorption ratio, and sheet resistivity were adapted to monitor phosphorous concentration indirectly Dielectric properties, step coverage, crack resistance, and gettering effect are discussed in both of atmospheric pressure CVD (APCVO) and PECVD oxide. PECVD SiO2 film have density of about 2.4 g/㎤ at deposition rate of 450$\AA$/min, refractive index of about 1.53, and breakdown at fields of II-13 MV/cm. Crack resistance of PECVD oxide is greater than APCVD oxide. PECVD PSG films contained with 2 mole % phosphorous show good step coverage and gettering ability. The obtained results show more advantages in PECVD PSG than in APCVD PSG for device passivation.

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