• Journal of Power Electronics
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• v.2 no.3
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• pp.162-170
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• 2002

Voltage sag detection algorithm for voltage sag corrector is proposed in this paper. To quantify the standard of voltage unbalance under the faulted conditions, the 3-phase unbalanced voltages are decomposed into two balanced 3-phase symmetrical components of the positive and negative sequence voltages, which is defined by the magnitude factor (MF) and unbalance factor (UF). It is analyzed that MWF and UF values are given as the dc constant values even though under the voltage unbalance condition. This paper also proposes the control scheme of the instantaneous voltage sag corrector based on this detection algorithm. The validity of the proposed algorithm is verified through the EMTDC simulation and experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.4
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• pp.327-334
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• 2010

This paper deals with a single-phase dynamic voltage restorer(DVR) with a quasi Z-source topology. The proposed system based on a single-phase quasi Z-source PWM ac-ac converter which have features such as the input voltage and output voltage are sharing ground, and input current operates in continuous current mode(CCM). For the detection of voltage sag-swell, peak voltage detection method is applied. Also, the circuit principles of the proposed system are described. During the 60% severe voltage sag and 30% voltage swell, the proposed system controls the adding or missing voltage and maintains the rated voltage of sinusoidal waveform at the terminals of the critical loads. Finally, PSIM simulation and experimental results are presented to verify the proposed concept and theoretical analysis.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.172-174
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• 2005

Recently, a concern of power qualify increases because of electronic device development and well-being generation. Power quality problems such as voltage sag, harmonics, flicker etc. have adverse effects on electric devices. Therefore, power quality problems have been monitored. This paper studies a detection of voltage sag that is more severer than the others. A voltage sag has been monitored using rms or wavelet method. This paper proposes an advance detection method using wavelet. An error Of Start Point differs error of ending point. We use this difference. So, we respectively revise detection error. Also, we revise multiplying average error rate.

• Corrosion Science and Technology
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• v.18 no.6
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• pp.277-284
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• 2019

External corrosion control of buried pipe can be achieved by the combination of barrier coating and cathodic protection. Coating damage and deterioration can be induced by many reasons; damage during handling and laying, enhanced failure at low temperatures, failure during commissioning and operation, disbanding due to inadequate surface cleaning, rock penetration during installation and service etc. This work focused on the effect of survey conditions on the reliability of coating flaw detection of buried pipes. The effects of applied voltage and anode location on the detection reliability of coating flaw of buried pipe in soil with the resistivity of ca. 25.8 kΩ·cm were discussed. Higher applied voltage increased the detection reliability, regardless of buried depth, but deeper burial depth reduced the reliability. The location of the anode has influenced on the detection reliability. This behaviour may be induced by the variation of current distribution by the applied voltage and buried depth. From the relationship between the applied voltage and reliability, the needed detection potential to get a desire detection reliability can be calculated to get 100% detection reliability using the derived equation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.12
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• pp.65-73
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• 2014

In this paper, the detection scheme of the voltage variation using a two difference voltage is proposed. The conventional sag detector is from a single-phase digital phase-locked loop (DPLL) that is based on a d-q transformation using an all-pass filter (APF). The APF generates a virtual q-axis voltage component with $90^{\circ}$ phase delay but the APF cannot generate the virtual q-axis voltage depending on the phase of the grid voltage. To overcome the problem, q-axis voltage component is generated from difference between the current and previous value of d-axis voltage component in the stationary reference frame. However, the difference voltage around the zero crossing is not enough to detect the voltage sag. Therefore, the new detection scheme using the two difference voltage which can detect the sag around the zero crossing voltage is proposed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.9
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• pp.425-432
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• 2000

Wavelet transform is a new method fro electric power quality analysis. Several types of mother wavelets are compared using voltage sag data. Investigations on the use of some mother wavelets, namely Daubechies, Symlets, Coiflets, Biorthogonal, are carried out. On the basis of extensive investigations, optimal mother wavelets for the detection of voltage sag are chosen. The recommended mother wavelet is 'Daubechies 4(db4)' wavelet. 'db4', the most commonly applied mother wavelet in the power quality analysis, can be used most properly in disturbance phenomena which occurs rapidly for a short time. This paper presents a discrete wavelet transform approach for determining the beginning time and end time of voltage sags. The technique is based on utilising the maximum value of d1(at scale 1) coefficients in multiresolution analysis(MRA) based on the discrete wavelet transform. The procedure is fully described, and the results are compared with other methods for determining voltage sag duration, such as the RMS voltage and STFT(Short-Time Fourier Transform) methods. As a result, the voltage sag detection using wavelet transform appears to be a reliable method for detecting and measuring voltage sags in power quality disturbance analysis.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.245-248
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• 2000

In this paper a novel method for voltage disturbance detection is presented. This is a instantaneous detection method using normalized error get in synchronous reference frame and also it is implemented in digital. Feedback noise the problem of digital implementation is removed by a digital filter of which the time delay is compensated through numerical analysis.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.6
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• pp.584-591
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• 2000

Power Quality Compensator(PQC) has been installed to protect the sensitive loads against the voltage disturbances, such as voltage sag and interruption. In general, static switch is used for the purpose of link between utility and PQC. So transfer operation of the static switch play a important part in the PQC. Many studies on the structure and control of PQC have been progressed in active, but these researches have been rarely mentioned about any voltage-disturbances-detection method to start the PQC operation. In this paper, a new voltage-disturbances-detection algorithm for computer application loads using the CBEMA/ITIC curve is proposed for transfer operation of the static switch. The proposed detection algorithm is implemented to get fast detecting time through the comparison of instantaneous 3-phase voltage values transferred to DC values in the synchronous reference frame with the operating reference values. To get the robust characteristics against the noise, a first order digital filter is designed. The magnitude falling and phase delay caused by the filter are compensated through the error normalizing and numerical analysis using transfer function, respectively. Finally, the validity of the proposed algorithm is proved by ACSL simulation and experimental results.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1513-1522
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• 2018

This paper proposes a new islanding detection method for inverter-based distributed generators by continuously injecting a negligible amount of 2nd order harmonic current. The proposed method adopts a proportional resonant (PR) controller for the output current control of the inverter, and a PR filter to extract the 2nd order harmonic voltage at the point of common coupling (PCC). The islanding state can be detected by measuring the magnitude ratio of the 2nd order harmonic voltage to the fundamental voltage at the PCC by injecting a 2nd order harmonic current with a 0.8% magnitude. The proposed method provides accurate and fast detection under grid voltage unbalance and load unbalance. The operation of the proposed method has been verified through simulations and experiments with a 5kW hardware set-up, considering the islanding test circuit suggested in UL1741.