• 융합신호처리학회논문지
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• 제3권3호
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• pp.63-69
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• 2002

디테일드 라우팅은 VLSI 설계 과정중의 하나로, 글로벌 라우팅을 수행한 후 각 라우팅 영역에 할당된 네트들을 트랙에 할당하여 구체적인 네트들의 위치를 결정하는 문제이며, 디테일드 라우팅에서 최적의 해를 얻기 위해 left-edge 알고리즘, dogleg 알고리즘, greedy 채널 라우팅 알고리즘등이 이용된다 본 논문에서는 디테일드 라우팅 문제에 대하여 유전자 알고리즘(genetic algorithm; GA)을 이용한 해 공간 탐색(solution space search) 방식을 제안하였으며, 제안한 방식을 greedy 채널 라우팅 알고리즘과 비교, 분석하였다.

• 전자공학회논문지A
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• 제30A권3호
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• pp.104-113
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• 1993

A new switchbox router, called CONQUEROR, is proposed in this paper. The proposed CONQUEROR efficiently routes large switchbox routing area using divide-and-conquer technique. The CONQUEROR consists of three phases` namely, partition of large routing area and assignment of optimal pins of sub-area, detailed routing of each sub-ared, reassignment of pins after rip-up. First, large switchbox routing area is partitioned into several sub-areas and each sub-area contains 4-6 detailed grids. Then pins are assigned on boundary of sub-area by the estimated weight. Secondly, when global pin assignment is completed on all sub-areas, each sub-area is routed using detailed router. Also, detailed routing consists of three pases` layerless maze routing, assignment of layer using coloring, and rip-up and reroute. Lastly, if detailed routing of any sub-area fails,reassignment of pins after rip-up is invoked. Detailed routing is performed for the failed sub-area again. Benchmark test cases have been run, and on all the benchmark data known in the literature CONQUEROR has performed as well as or better than existing switchbox routers.

• 전자공학회논문지C
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• 제34C권10호
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• pp.8-18
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• 1997

In FPGAs, we may use the property of the routing architecture for their routing compared to the routing in the conventional layout style. Especially, the Xilinx XC4000 series FPGAs have very special routing architecture in which the routing problem is equivalent to the two dimensional track assignment problem. In this paper, we propose a new FPgA detailed routing method by developing a two dimensional trackassigment heuristic algorithm. The proposed routing mehtod accept a global routing result as an input and obtain a detailed routing such that the number of necessary wire segments in each connection block is minimized. For all benchmark circuits tested, our routing methd complete routing results. The number of used tracks are also similar to the results by thedirect routing methods.

• 대한전자공학회논문지
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• 제27권4호
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• pp.628-635
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• 1990

This paper describes a new gate array layout system, HAN-LACAD-G(HANyang LAyout CAD system for Gate array). HAN-LACAD-G is composed of placer, global router, detailed router, and output processor. In placement design, initial placement is performed by repetitive clustering and min-cut partitioning followed by placement improvement using the concept of pairwise interchange. In global routing phase, pins are assigned in each channel considering the routing congestion estimation and overflows in feedthroughs are restricted. For the detailed routing, we use layer and three layer channel routing techniques. Layout results are displayed graphically and modified interactively by the user using the layout editor.

• 대한전자공학회논문지
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• 제22권3호
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• pp.60-67
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• 1985

본 논문에서는 VLSI layout CAD에 있어서의 새로운 그로발 라우팅(global routing) 기법을 제안하고 이에 관하여 논하였다. 종래의 그로발 라우터에서는 핀의 위치를 모두 셀의 중앙에 두었기 때문에 신호선의 채널 사용량을 정확히 산출할 수 없었다. 그 결과 디테일드 라우팅 (detailed routing)시 배선량 overflow가 발생하여 100% 결선을 저해하는 많은 요인을 내포하고 있었다. 본 논문에서는 이러한 문제점을 모두 보완하기 위하여 핀순서를 고려한 새로운 방법의 그로발 라우팅 알고리즘을 제안하였다. 이 알고리즘을 사용하여 그로발 라우터를 실현하고, 계산기상의 실험 결과를 통하여 제안한 알고리즘의 유용성을 보였다.

• 대한전자공학회논문지
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• 제25권5호
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• pp.572-579
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• 1988

In this paper, a system of automatic placement and routing for gate array layout design is proposed. In the placement stage, the circuit is partitioned and using the concept of min-cut slicing, and each partitioned module is placed, so that the routing density over the entire chip be uniformized and the total wiring length be minimized. In the global routing stage, the concept of the probabilistic routing density is introduced to unify the wiring congestions in each channel. In the detailed routing stage, the multi-terminal nets are partitioned into the two-terminal nets. The ordered channel graph is proposed which implies the vertical and the horizontal constranint graphs simultaneously. And using the ordered channel graph, the proposed routing algorithm assigns the signal nets to the tracks. Also the proposed placement and routing algorithms are implimented on IBM/PC-AT to construct PC-level gate array layout system.

• 대한전자공학회논문지
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• 제26권5호
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• pp.145-151
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• 1989

본 논문에서는 semi-custom 방식의 레이아웃 설계중 게이트 배선 설계에서 배선의 효율을 높이기 위한 전처리 과정에 대해 논한다. Global 배선 설계의 결과로 주어진 각 채널에서의 핀 정보중 논리적으로 등가인 핀의 위치를 교환함으로써 detailed 배선에서 발생하는 싸이클을 해소할 수 있으며, 신호선의 분할에 의해 이웃하는 채널에서 중복으로 연결되는 신호선이 제거됨으로써 트랙수의 증가를 억제한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1732-1735
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• 2002

A $\kappa$-side switch box with W terminals on each side is said to be hyper universal, denoted by ($\kappa$, W)-HUSB, if it is routable for any global .outing with density at most W. In [5], we have proposed a switch box design strategy and designed a near optimum (4, W)-HUSB F(W) with 6.W switches. In this paper, we design, analyze and implement an efficient detailed routing algorithm for the S-box F(W). This router. can accommodate all routing requirement topologies.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2007년도 춘계학술발표대회
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• pp.873-874
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• 2007

In this paper, we make a detailed study about the routing related energy consumption problem in Wireless Sensor Networks. Based on this study, we present the selection criterion of the intermediate nodes so as to make the routing problem energy-efficient. Experimental results are provided with reasonable verification.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제3권1호
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• pp.52-83
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• 2009

In this technical report, we have examined the basic building blocks of mobile ad-hoc networks. The paper discusses various security requirements of ad-hoc networks, attacks in ad-hoc networks, Security Implementation and Routing Protocols. The primary purpose of the paper is to address the Optimized Link State Routing (OLSR) protocol in detail, along with the various possible attacks. Finally, algorithms for securing OLSR are proposed, via the addition of digital signatures, as well as more advanced techniques such as cross checking of advertised routing control data with the node's geographical position. The main aim of this research work is the addition of security features to the existing OLSR protocol. In order to effectively design a secure routing protocol, we present a detailed literature survey of existing protocols, along with the various attacks. Based on the information gathered from the literature survey, a secure routing protocol for OLSR is proposed. The proposed secure routing protocol involves the addition of a digital signature as well as more advanced techniques such as the reuse of previous topology information to validate the actual link state. Thus, the main objective of this work is to provide secure routing and secure data transmission.