• Journal of the Institute of Convergence Signal Processing
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• v.3 no.3
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• pp.63-69
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• 2002

Detailed routing is a problem assigning each net to a track after global routing. The most popular algorithms for detailed routing include left-edge algorithm, dogleg algorithm, and greedy channel routing algorithm. In this paper we propose a genetic algorithm searching solution space for the detailed routing problem. We compare the performance of proposed genetic algorithm(GA) for detailed routing with that of greedy channel routing algorithm by analyzing the results of each implementation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.104-113
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• 1993

A new switchbox router, called CONQUEROR, is proposed in this paper. The proposed CONQUEROR efficiently routes large switchbox routing area using divide-and-conquer technique. The CONQUEROR consists of three phases` namely, partition of large routing area and assignment of optimal pins of sub-area, detailed routing of each sub-ared, reassignment of pins after rip-up. First, large switchbox routing area is partitioned into several sub-areas and each sub-area contains 4-6 detailed grids. Then pins are assigned on boundary of sub-area by the estimated weight. Secondly, when global pin assignment is completed on all sub-areas, each sub-area is routed using detailed router. Also, detailed routing consists of three pases` layerless maze routing, assignment of layer using coloring, and rip-up and reroute. Lastly, if detailed routing of any sub-area fails,reassignment of pins after rip-up is invoked. Detailed routing is performed for the failed sub-area again. Benchmark test cases have been run, and on all the benchmark data known in the literature CONQUEROR has performed as well as or better than existing switchbox routers.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.8-18
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• 1997

In FPGAs, we may use the property of the routing architecture for their routing compared to the routing in the conventional layout style. Especially, the Xilinx XC4000 series FPGAs have very special routing architecture in which the routing problem is equivalent to the two dimensional track assignment problem. In this paper, we propose a new FPgA detailed routing method by developing a two dimensional trackassigment heuristic algorithm. The proposed routing mehtod accept a global routing result as an input and obtain a detailed routing such that the number of necessary wire segments in each connection block is minimized. For all benchmark circuits tested, our routing methd complete routing results. The number of used tracks are also similar to the results by thedirect routing methods.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.628-635
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• 1990

This paper describes a new gate array layout system, HAN-LACAD-G(HANyang LAyout CAD system for Gate array). HAN-LACAD-G is composed of placer, global router, detailed router, and output processor. In placement design, initial placement is performed by repetitive clustering and min-cut partitioning followed by placement improvement using the concept of pairwise interchange. In global routing phase, pins are assigned in each channel considering the routing congestion estimation and overflows in feedthroughs are restricted. For the detailed routing, we use layer and three layer channel routing techniques. Layout results are displayed graphically and modified interactively by the user using the layout editor.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.3
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• pp.60-67
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• 1985

A new glut bel routing technique for gate array is described in this paper. In former global routers the position of pins is considered to be in the center of the cell. So it is impossible to exactly estimate the number of signal lines passing through each channel. As a result, an overflow occurs and the overflow violates 100% wiring in detailed routing pro-cesses. Besides this, there are some problems in former global routers, for example, design time and cost, etc. This paper proposed a new algorithm in which pins ordering is considered to solve these problems. Using this algorithm, a global router is developed. Program experiments show the efficiency of the proposed algorithm.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.572-579
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• 1988

In this paper, a system of automatic placement and routing for gate array layout design is proposed. In the placement stage, the circuit is partitioned and using the concept of min-cut slicing, and each partitioned module is placed, so that the routing density over the entire chip be uniformized and the total wiring length be minimized. In the global routing stage, the concept of the probabilistic routing density is introduced to unify the wiring congestions in each channel. In the detailed routing stage, the multi-terminal nets are partitioned into the two-terminal nets. The ordered channel graph is proposed which implies the vertical and the horizontal constranint graphs simultaneously. And using the ordered channel graph, the proposed routing algorithm assigns the signal nets to the tracks. Also the proposed placement and routing algorithms are implimented on IBM/PC-AT to construct PC-level gate array layout system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.145-151
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• 1989

A new preprocess technique is presented which can improve the routing efficiency in the gate array layout designs. In order to resolve the cycle problem in the detailed routing, we exchange the logically equivalent pins in each channel. The signal nets are divided, and doubly connected signal net components are removed, so that the increase in the number of tracks can be controlled.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1732-1735
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• 2002

A $\kappa$-side switch box with W terminals on each side is said to be hyper universal, denoted by ($\kappa$, W)-HUSB, if it is routable for any global .outing with density at most W. In [5], we have proposed a switch box design strategy and designed a near optimum (4, W)-HUSB F(W) with 6.W switches. In this paper, we design, analyze and implement an efficient detailed routing algorithm for the S-box F(W). This router. can accommodate all routing requirement topologies.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.873-874
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• 2007

In this paper, we make a detailed study about the routing related energy consumption problem in Wireless Sensor Networks. Based on this study, we present the selection criterion of the intermediate nodes so as to make the routing problem energy-efficient. Experimental results are provided with reasonable verification.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.3 no.1
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• pp.52-83
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• 2009

In this technical report, we have examined the basic building blocks of mobile ad-hoc networks. The paper discusses various security requirements of ad-hoc networks, attacks in ad-hoc networks, Security Implementation and Routing Protocols. The primary purpose of the paper is to address the Optimized Link State Routing (OLSR) protocol in detail, along with the various possible attacks. Finally, algorithms for securing OLSR are proposed, via the addition of digital signatures, as well as more advanced techniques such as cross checking of advertised routing control data with the node's geographical position. The main aim of this research work is the addition of security features to the existing OLSR protocol. In order to effectively design a secure routing protocol, we present a detailed literature survey of existing protocols, along with the various attacks. Based on the information gathered from the literature survey, a secure routing protocol for OLSR is proposed. The proposed secure routing protocol involves the addition of a digital signature as well as more advanced techniques such as the reuse of previous topology information to validate the actual link state. Thus, the main objective of this work is to provide secure routing and secure data transmission.