• 제목/요약/키워드: designing area in the semiconductor engineering

검색결과 4건 처리시간 0.02초

High-Isolation SPDT RF Switch Using Inductive Switching and Leakage Signal Cancellation

  • Ha, Byeong Wan;Cho, Choon Sik
    • Journal of electromagnetic engineering and science
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    • 제14권4호
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    • pp.411-414
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    • 2014
  • A switch is one of the most useful circuits for controlling the path of signal transmission. It can be added to digital circuits to create a kind of gate-level device and it can also save information into memory. In RF subsystems, a switch is used in a different way than its general role in digital circuits. The most important characteristic to consider when designing an RF switch is keeping the isolation as high as possible while also keeping insertion loss as low as possible. For high isolation, we propose leakage signal cancellation and inductive switching for designing a singlepole double-throw (SPDT) RF switch. By using the proposed method, an isolation level of more than 23 dB can be achieved. Furthermore, the heterojunction bipolar transistor (HBT) process is used in the RF switch design to keep the insertion loss low. It is demonstrated that the proposed RF switch has an insertion loss of less than 2 dB. The RF switch operates from 1 to 8 GHz based on the $0.18-{\mu}m$ SiGe HBT process, taking up an area of $0.3mm^2$.

Morphology control of inkjet-printed small-molecule organic thin-film transistors with bank structures

  • Kim, Yong-Hoon;Park, Sung-Kyu
    • Journal of Information Display
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    • 제12권4호
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    • pp.199-203
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    • 2011
  • Reported herein is the film morphology control of inkjet-printed 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) organic thin-film transistors for the improvement of their performance and of the device-to-device uniformity. The morphology of the inkjetted TIPS-pentacene films was significantly influenced by the bank geometry such as the bank shapes and confinement area for the channel region. A specific confinement size led to the formation of uniform TIPS-pentacene channel layers and better electrical properties, which suggests that the ink volume and the solid concentration of the organic-semiconductor solutions should be considered in designing the bank geometry.

반도체분야 공과대학 산업기여도 평가 사례 연구 (A Case Study of the Evaluation on the Contribution Made by Engineering Colleges to Industry - Particularly in the Field of Semiconductor Technology)

  • 박종성;주인중;김현수;정연배
    • 공학교육연구
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    • 제12권4호
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    • pp.18-29
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    • 2009
  • 본 연구는 반도체 설계 공정 분야에서 요구하는 지식과 스킬에 대하여 공과대학의 교육과정이 어느 정도 반영하고 있는지를 분석하기 위해 수행하였다. 공과대학 산업기여도 평가를 실시한 결과 산업계에서 요구하는 지식과 관련된 내용은 교육과정 반영정도는 높으나, 스킬과 관련된 내용은 반영정도는 낮았고, 산업계에서 요구하는 지식과 스킬이 대학에서 교과목으로 개설된 정도에 비해 졸업생들의 이수정도는 매우 낮은 것으로 나타났다. 산업계 요구 지식 스킬에 대한 졸업생의 업무활용 만족도는 상대적으로 높았고, 기초역량에 비하여 직무역량이 대학교육에서의 습득정도가 다소 낮았으며, 대학별 평가결과, 학교간의 역점을 두는 교육과정에 차이가 있는 것으로 나타났다.

An Efficient Technique to Protect AES Secret Key from Scan Test Channel Attacks

  • Song, Jae-Hoon;Jung, Tae-Jin;Jung, Ji-Hun;Park, Sung-Ju
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제12권3호
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    • pp.286-292
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    • 2012
  • Scan techniques are almost mandatorily adopted in designing current System-on-a-Chip (SoC) to enhance testability, but inadvertently secret keys can be stolen through the scan test channels of crypto SoCs. An efficient scan design technique is proposed in this paper to protect the secret key of an Advanced Encryption Standard (AES) core embedded in an SoC. A new instruction is added to IEEE 1149.1 boundary scan to use a fake key instead of user key, in which the fake key is chosen with meticulous care to improve the testability as well. Our approach can be implemented as user defined logic with conventional boundary scan design, hence no modification is necessary to any crypto IP core. Conformance to the IEEE 1149.1 standards is completely preserved while yielding better performance of area, power, and fault coverage with highly robust protection of the secret user key.