• Title/Summary/Keyword: designing area in the semiconductor engineering

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High-Isolation SPDT RF Switch Using Inductive Switching and Leakage Signal Cancellation

  • Ha, Byeong Wan;Cho, Choon Sik
    • Journal of electromagnetic engineering and science
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    • v.14 no.4
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    • pp.411-414
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    • 2014
  • A switch is one of the most useful circuits for controlling the path of signal transmission. It can be added to digital circuits to create a kind of gate-level device and it can also save information into memory. In RF subsystems, a switch is used in a different way than its general role in digital circuits. The most important characteristic to consider when designing an RF switch is keeping the isolation as high as possible while also keeping insertion loss as low as possible. For high isolation, we propose leakage signal cancellation and inductive switching for designing a singlepole double-throw (SPDT) RF switch. By using the proposed method, an isolation level of more than 23 dB can be achieved. Furthermore, the heterojunction bipolar transistor (HBT) process is used in the RF switch design to keep the insertion loss low. It is demonstrated that the proposed RF switch has an insertion loss of less than 2 dB. The RF switch operates from 1 to 8 GHz based on the $0.18-{\mu}m$ SiGe HBT process, taking up an area of $0.3mm^2$.

Morphology control of inkjet-printed small-molecule organic thin-film transistors with bank structures

  • Kim, Yong-Hoon;Park, Sung-Kyu
    • Journal of Information Display
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    • v.12 no.4
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    • pp.199-203
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    • 2011
  • Reported herein is the film morphology control of inkjet-printed 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) organic thin-film transistors for the improvement of their performance and of the device-to-device uniformity. The morphology of the inkjetted TIPS-pentacene films was significantly influenced by the bank geometry such as the bank shapes and confinement area for the channel region. A specific confinement size led to the formation of uniform TIPS-pentacene channel layers and better electrical properties, which suggests that the ink volume and the solid concentration of the organic-semiconductor solutions should be considered in designing the bank geometry.

A Case Study of the Evaluation on the Contribution Made by Engineering Colleges to Industry - Particularly in the Field of Semiconductor Technology (반도체분야 공과대학 산업기여도 평가 사례 연구)

  • Park, Jong-Sung;Ju, In-Joong;Kim, Hyun-Soo;Jeong, Yeon-Bae
    • Journal of Engineering Education Research
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    • v.12 no.4
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    • pp.18-29
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    • 2009
  • The main objective of this study is to provide necessary information to improve the college curriculums to reflect the demands from the industry. As a result of the evaluation on the contribution of the engineering colleges to industries, we found out that the knowledge required in the industry was well reflected in contents of college curriculums and the number of college graduates who took the curriculums that contain knowledge and skills required in the industry was very small compared to the number of courses established in colleges. The satisfaction rate on practical application of the knowledge and skills at the work was relatively high. According to the result of evaluating curriculums of different colleges it was found out that the areas where colleges put their key focus were different by schools.

An Efficient Technique to Protect AES Secret Key from Scan Test Channel Attacks

  • Song, Jae-Hoon;Jung, Tae-Jin;Jung, Ji-Hun;Park, Sung-Ju
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.3
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    • pp.286-292
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    • 2012
  • Scan techniques are almost mandatorily adopted in designing current System-on-a-Chip (SoC) to enhance testability, but inadvertently secret keys can be stolen through the scan test channels of crypto SoCs. An efficient scan design technique is proposed in this paper to protect the secret key of an Advanced Encryption Standard (AES) core embedded in an SoC. A new instruction is added to IEEE 1149.1 boundary scan to use a fake key instead of user key, in which the fake key is chosen with meticulous care to improve the testability as well. Our approach can be implemented as user defined logic with conventional boundary scan design, hence no modification is necessary to any crypto IP core. Conformance to the IEEE 1149.1 standards is completely preserved while yielding better performance of area, power, and fault coverage with highly robust protection of the secret user key.