• Title/Summary/Keyword: delay-line

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Analysis and Design of High Efficiency Feedforward Amplifier Using Distributed Element Negative Group Delay Circuit (분산 소자 형태의 마이너스 군지연 회로를 이용한 고효율 피드포워드 증폭기의 분석 및 설계)

  • Choi, Heung-Jae;Kim, Young-Gyu;Shim, Sung-Un;Jeong, Yong-Chae;Kim, Chul-Dong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.6
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    • pp.681-689
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    • 2010
  • We will demonstrate a novel topology for the feedforward amplifier. This amplifier does not use a delay element thus providing an efficiency enhancement and a size reduction by employing a distributed element negative group delay circuit. The insertion loss of the delay element in the conventional feedforward amplifier seriously degrades the efficiency. Usually, a high power co-axial cable or a delay line filter is utilized for a low loss, but the insertion loss, cost and size of the delay element still acts as a bottleneck. The proposed negative group delay circuit removes the necessity of the delay element required for a broadband signal suppression loop. With the fabricated 2-stage distributed element negative group delay circuit with -9 ns of total group delay, a 0.2 dB of insertion loss, and a 30 MHz of bandwidth for a wideband code division multiple access downlink band, the feedforward amplifier with the proposed topology experimentally achieved a 19.4 % power added efficiency and a -53.2 dBc adjacent channel leakage ratio with a 44 dBm average output power.

A Speed-Based Dijkstra Algorithm for the Line Tracer Control of a Robot (로봇 경로 제어를 위한 속도기반 Dijkstra 알고리즘)

  • Cheon, Seong-Kwon;Kim, Geun-Deok;Kim, Chong-Gun
    • Journal of Information Technology Services
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    • v.10 no.4
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    • pp.259-268
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    • 2011
  • A robot education system by emulation based on Web can be efficiently used for understanding concept of robot assembly practice and control mechanism of robot by control programming. It is important to predict the path of the line tracer robot which has to be decided by the robot. Shortest Path Algorithm is a well known algorithm which searches the most efficient path between the start node and the end node. There are two related typical algorithms. Dijkstra Algorithm searches the shortest path tree from a node to the rest of the other nodes. $A^*$ Algorithm searches the shortest paths among all nodes. The delay time caused by turning the direction of navigation for the line tracer robot at the crossroads can give big differences to the travel time of the robot. So we need an efficient path determine algorithm which can solve this problem. Thus, It is necessary to analyze the overhead of changing direction of robot at multi-linked node to determine the next direction for efficient routings. In this paper, we reflect the real delay time of directional changing from the real robot. A speed based Dijkstra algorithm is proposed and compared with the previous ones to analyze the performance.

Optimizing the design factors of the head-fed type combine(I) -Estimation of the threshing drum torque curve- (자탈형 콤바인 탈곡부 설계요인(設計要因)의 적정화(適正化)를 위한 연구(I) -급동축(扱胴軸) 토오크 파형의 추정(推定)-)

  • Nam, S.I.;Chung, C.J.;Hosokawa, A.
    • Journal of Biosystems Engineering
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    • v.12 no.3
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    • pp.42-49
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    • 1987
  • The threshing action of the head-fed type threshing unit occurs mainly by the impact between threshing tooth and grains. It may be therefore the most fundamental step to calculate the time and order of the occurrance of impact by the tooth for predicting the performance of threshing unit. The threshing teeth arrangement was defined by length and diameter of threshing dram, number of spiral arrays, number of threshing teeth by kind per one spiral array, number of windings of spiral array around the threshing drum, delay angle of impact line. The linear equations for locus of left and right margin of paddy bundle, spiral array, impact line on the development figure of the threshing drum were expressed by fastors of the threshing teeth arrangement. In the computer program, the teeth which inflict impact were searched successively along the impact line. Searching range and impact condition were defined by the relation between four linear equations. If the impacting tooth was found, time and the kind of threshing tooth was derived from the coordinate of the threshing tooth. At this time the unit torque curve was accumulated on the array of computer memory. At last the completed torque curve of threshing drum shaft was described on the computer screen. Remarkably the peack valae and fluctuation of torque curve was decreased by adopting the delay angle of impact line.

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Wide-Beam Circularly Polarized Crossed Scythe-Shaped Dipoles for Global Navigation Satellite Systems

  • Ta, Son Xuat;Han, Jea Jin;Park, Ikmo;Ziolkowski, Richard W.
    • Journal of electromagnetic engineering and science
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    • v.13 no.4
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    • pp.224-232
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    • 2013
  • This paper describes composite cavity-backed crossed scythe-shaped dipoles with wide-beam circularly polarized (CP) radiation for use in Global Navigation Satellite Systems. Each branch of the dipole arm contains a meander line, with the end shaped like a scythe to achieve a significant reduction in the size of the radiator. For dual-band operation, each dipole arm is divided into two branches of different lengths. The dipoles are crossed through a $90^{\circ}$ phase delay line of a vacant-quarter printed ring to achieve CP radiation. The crossed dipoles are incorporated with a cavity-backed reflector to make the CP radiation unidirectional and to improve the CP radiation beamwidth. The proposed antennas have broad impedance matching and 3-dB axial ratio bandwidths, as well as right-hand CP radiation with a wide-beamwidth and high front-to-back ratio.

A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

  • Kim, Sung-Yong;Jin, Xuefan;Chun, Jung-Hoon;Kwon, Kee-Won
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.4
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    • pp.387-394
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    • 2016
  • This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

Efficient Multicast Tree Algorithm for Acceptable Delay and Minimum Delay Variation (지연시간 한계의 만족과 효율적인 최소 지연변이 멀티캐스트 트리 생성 알고리즘)

  • Kim Moon-Seong;Choo Hyun-Seung;Lee Young-Ro
    • The KIPS Transactions:PartC
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    • v.12C no.1 s.97
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    • pp.105-110
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    • 2005
  • With the proliferation of multimedia group applications, the construction of multicast trees satisfying QoS requirements is becoming a problem of prime importance. In this paper, we study the delay- and delay variation-bounded multicast tree (DVBMT) problem which is NP-complete. The problem is to construct a spanning tree for destination node, which has the minimized multicast delay variation, and the delay on the path from the source to each destination is bounded. A solution to this problem is required to provide decent real-time communication services such as on-line games, shopping, and teleconferencing. Performance comparison shows that the proposed scheme outperforms DDVCA which is known to be effective so far in any network topology. The enhancement is up to about $3.6{\%}{\~}11.1{\%}$ in terms of normalized surcharge for DUVCA. The time complexity of our algorithm is $O(mn^2)$.

Improving the Accuracy of the Tapped Delay Time-to-Digital Converter Using Field Programmable Gate Array (Field-Programmable Gate Array를 사용한 탭 딜레이 방식 시간-디지털 변환기의 정밀도 향상에 관한 연구)

  • Jung, Do-Hwan;Lim, Hansang
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.9
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    • pp.182-189
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    • 2014
  • A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.

An effects of the Pulse Distortion due to Dispersion and Reflection on Tapered Microstrip Line (데이퍼형 마이크로 스트립 선로에서 분산과 반사가 펄스의 왜곡에 미치는 영향)

  • 김기래
    • Proceedings of the IEEK Conference
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    • 2000.06a
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    • pp.271-274
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    • 2000
  • In this paper, the distortion of an electrical pulse with rise/fall time resulting from dispersion and reflection as it propagates along a tapered microstrip line is investigated, and the delay time and distortion rate with respect to input and load impedances are analyzed on triangular and exponential tapered lines and analyzed the influence of the reflection and frequency dispersion on the distorted voltage wave in the tapered lines. The observed overshoot in front of the distorted wave is caused due to the frequency dispersion and the sustained tail of that comes from the reflection in the tapered line.

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On-Line Identification Algorithm for Unknown Linear MIMO Systems (미지의 선형 MIMO 시스템에 대한 On-Line 모델링 알고리즘)

  • 최수일;김병국
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.7
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    • pp.58-65
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    • 1994
  • A recursive on-line algorithm for orthogonal ARMA identification is proposed for linear MIMO systems with unknown parameters time delay and order. This algorithm is based on the Gram-Schmidt orthogonalization of basis functions, and extended to a recursiveform by using new functions of two dimensional autocorrelations and crosscorrelations of inputs and outputs. This proposed algorithm can also cope with slowly time-varying or order-varying systems. Various simulations reveal the performance of the algorithm.

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On-line identification algorithm for unknown linear MIMO systems (미지의 선형 MIMO 시스템에 대한 On-line 모델링 알고리즘)

  • 최수일;김병국
    • 제어로봇시스템학회:학술대회논문집
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    • 1993.10a
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    • pp.58-63
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    • 1993
  • A recursive on-line algorithm with orthogonal ARMA identification is proposed for linear MIMO systems with unknown parameters, time delay, and order. This algorithm is based on the Gram-Schmidt orthogonalization of basis functions, and extended to a recursive form by using new functions of two dimensional autocorrelations and cross-correlations of inputs and outputs. The proposed algorithm can also cope with slowly time-varying or order-varying systems. Various simulations reveal the performance of the algorithm.

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