• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.723-726
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• 1998

Fault dropping is a very important part of test generation process. It is used to reduce test generation time. Test generation systems use fault simulation for the purpose of fault dropping by identifying detectable faults with generated test patterns. Two kinds of delay fault model is used in practice, path delay fault model and gate delay fault model. In this paper we propose an efficient method for gate delay test generation which shares second test vector.

• 전자공학회논문지A
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• 제31A권6호
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• 전자공학회논문지A
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• 제33A권2호
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• pp.205-216
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• 1996

In this paper we propose an efficient robust path delay fault test genration algorithm for detection of path delay faluts in combinational ligic circuits. In the proposed robust test genration approach, the testability measure is computed for all gates in the circuit under test and these computed values are used to genrate weighted random delay test vetors for detection of path delay faults. For genrated robust test vectors, we perform fault simulation on ISCAS '85 benchmark circuits using parallel pattern technqieus. The results indicate that the proposed test genration method not only increases the number of detected robust path delay faults but also reduces the time taen to genrate robust tests.

• 한국컴퓨터정보학회논문지
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• 제4권1호
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• pp.28-37
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• 1999

본 논문에서는 클록 입력을 갖는 대표적인 회로인 5비트 카운터를 대상회로로 선정하여 경계면 스캔 구조를 적용하고, 대상회로에 대한 지연시험을 위한 새로운 시험 구조와 지연시험 절차를 개발하였다. 지연시험 대상회로가 클록 입력을 갖는 경우, 기존의 경계면 스캔 구조에서는 동일한 패턴의 중복 입력, 클록 입력과 데이터 입력과의 시간 간격과, 패턴 입력과 응답값 캡쳐까지의 시간 문제에 의해 적절치 않음을 보였다. 본 논문에서 제안하는 지연 시험 구조는 클록 계수 발생기를 사용하여 연속 발생시킬 클록의 개수를 입력받아 이를 대상회로의 클록 입력에 적용하여 대상회로에 대한 입력 패턴의 중복문제를 해결하였다. 또한 시스템 클록을 TCK로 사용하여 대상회로를 정상 속도에서 동작할 수 있도록 하였다. 연속적인 클록 발생에 TCK를 사용함으로써 대상회로를 정상 속도에서 검증할 수 있다. 제안된 시험 구조와 절차는 대상회로에 대한 타이밍 시뮬레이션을 통해 동작의 정확성을 확인하였다.

• 대한전자공학회논문지SD
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• 제41권11호
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• pp.69-77
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• 2004

본 논문에서는 ground bounce 영향과 지연고장 검출을 함께 고려한 효율적인 보드레벨 연결선 테스트 생성 알고리즘을 제안한다. 제안된 알고리즘은 IEEE 1149.1의 연결선 테스트, ground bounce 영향에 의한 바운더리 스캔의 오동작 방지, 그리고 연결선의 지연고장 검출 능력을 포함한다. 본 논문에서 제안하는 기법은 기존의 기법에 비해 연결선의 지연고장 검출능력을 새롭게 추가하였지만, 연결선 테스트에 필요한 총 테스트 패턴 수는 기존의 기법과 비교해서 큰 차이를 보이지 않음을 실험결과에서 확인할 수 있다.

• 아동학회지
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• 제29권3호
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• pp.339-356
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• 2008

Participants in this study on preschool children's ability to delay gratification were 132 4- to 5 year-old children and their mothers from 6 daycare centers. Mothers completed questionnaires reporting their parenting style, their child's ability to delay gratification, and child's temperament. Children participated in the real and hypothetical settings of the delay of gratification experiment. Data was analyzed by t-test, F-test, correlation and discrimination analysis. Results were that (1) 43% of preschoolers passed the delay of gratification experiment. (2) Older children were more able to delay gratification than younger children. (3) Children's rewards choices in the real setting correlated with their rewards choices in the hypothetical situation of delay of gratification. (4) Children's ability to delay gratification was influenced by their motor intelligence.

• 전자공학회논문지C
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• 제35C권2호
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• pp.10-21
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• 1998

In this paper, we analyze the problems of conventional and previous mehtod on delay test method in IEEE 1149.1. To solve them, we propose two kinds of delay test architectures. One is called ARCH-C, is for combinatonal circuit, and the other is ARCH-S, for clocked sequential circuit. ARCH-C is able to detect delay defect of 0.5 $T_{tck}$ or 1 $T_{tck}$ size. And ARCH-C have a fixed and small amount of hardware overhead, on the contrary preious method has a hardware overhead on the dependent of CUT. This paper discusses weveral problems of Delay test on IEEE 1149.1 for clocked sequential circuit. We suggest the method called ARCH-S, is based on a clock counting technique to generate continuous clocked input of CUT. the simulation results ascertain the accurate operation and effectiveness of the proposed architectures.res.

• 가정과삶의질연구
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• 제24권3호
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• pp.15-25
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• 2006

This study has been performed to identify intelligent ability, reward choice in assumed situation of delay of gratification, and delay of gratification ability. The subjects for this study were 100 preschoolers between the ages of 4 and 5, their mothers, and 15 teachers of three day-care centers in Seoul. T-test, F-test, Correlation analysis and multiple regression analysis were used for data analysis. The main results of this study were as follows: First, preschoolers' delay of gratification ability by mothers' educational background was significant and delay of gratification ability by sex was significant. This means that mothers who had a higher educational background were positively related to preschoolers' delay of gratification ability. Second, in an assumed situation of delay of gratification, preschoolers' delay of gratification ability by reward choice was not significant. Third, delay of gratification by intelligent ability was significant. Fourth, the correlation among intelligent ability, reward choice in assumed situation of delay of gratification and delay of gratification ability were significant. Finally, preschoolers' delay of gratification ability was significantly influenced by two factors: reward choice in assumed situation of delay of gratification and preschoolers' intelligent ability.

• ETRI Journal
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• 제23권3호
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• pp.138-149
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• 2001

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

• Journal of Preventive Medicine and Public Health
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• 제26권4호
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• pp.650-660
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• 1993

This study aims to describe the causes of medically unnecessary hospital stay at a teaching tertiary hospital, using modified version of Delay Tool in which the causes of delay are divided into slx major categories : delay related to test scheduling, test results, surgery, medical staff, patient/family, and administration. For the analysis of hospital stay, 6,479 inpatient-days were reviewed in two medical and four surgical departments for one month. Initially inappropriate hospital stays were identified using Appropriateness Evaluation Protocol (AEP), and causes of delay listed in Delay Tool were assigned to each of them. In both medical and surgical services, the most important cause of delay was related to medical staffs, ranging from 3.6% to 51.6% of total inpatient days. Next important category was delay related to test scheduling in medical services ($4.7{\sim}9.2%$), and delay related to surgery in surgical services ($7.3{\sim}15.0%$). Among subcategories of delay related to medical staffs, delay due to conservative care was the most important cause of inappropriate hospital stay ($2.9{\sim}6.4%$). Each clinical departments had different distribution among delay categories, which could not be fully justified by their clinical charateristics. The Delay Tool would be helpful in exploring factors related to the inefficient use of hospital beds. As a measurement tool of inappropriate hospital stay, however, the Delay Tool should be refined in the definitions of categories and its contents.