• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.723-726
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• 1998

Fault dropping is a very important part of test generation process. It is used to reduce test generation time. Test generation systems use fault simulation for the purpose of fault dropping by identifying detectable faults with generated test patterns. Two kinds of delay fault model is used in practice, path delay fault model and gate delay fault model. In this paper we propose an efficient method for gate delay test generation which shares second test vector.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.205-216
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• 1996

In this paper we propose an efficient robust path delay fault test genration algorithm for detection of path delay faluts in combinational ligic circuits. In the proposed robust test genration approach, the testability measure is computed for all gates in the circuit under test and these computed values are used to genrate weighted random delay test vetors for detection of path delay faults. For genrated robust test vectors, we perform fault simulation on ISCAS '85 benchmark circuits using parallel pattern technqieus. The results indicate that the proposed test genration method not only increases the number of detected robust path delay faults but also reduces the time taen to genrate robust tests.

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.28-37
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• 1999

In this paper. we developed a delay test architecture and test procedure for clocked 5-bit asynchronous counter circuit based on boundary scan architecture. To develope, we analyze the problems of conventional method on delay test for clocked sequential circuit in boundary scan architecture. This paper discusses several problems of delay test on boundary scan architecture for clocked sequential circuit. Conventional test method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a delay test architecture and test procedure, is based on a clock count-generation technique to generate continuous clocks for clocked input of CUT. The simulation results or 5-bit counter shows the accurate operation and effectiveness of the proposed delay test architecture and procedure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.69-77
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• 2004

An efficient board-level interconnect test algorithm is proposed considering both the ground bounce effect and the delay fault detection. The proposed algorithm is capable of IEEE 1149.1 interconnect test, negative ground bounce effect prevention, and also detects delay faults as well. The number of final test pattern set is not much different with the previous method, even our method enables to detect the delay faults in addition to the abilities the previous method guarantees.

• Korean Journal of Child Studies
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• v.29 no.3
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• pp.339-356
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• 2008

Participants in this study on preschool children's ability to delay gratification were 132 4- to 5 year-old children and their mothers from 6 daycare centers. Mothers completed questionnaires reporting their parenting style, their child's ability to delay gratification, and child's temperament. Children participated in the real and hypothetical settings of the delay of gratification experiment. Data was analyzed by t-test, F-test, correlation and discrimination analysis. Results were that (1) 43% of preschoolers passed the delay of gratification experiment. (2) Older children were more able to delay gratification than younger children. (3) Children's rewards choices in the real setting correlated with their rewards choices in the hypothetical situation of delay of gratification. (4) Children's ability to delay gratification was influenced by their motor intelligence.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.10-21
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• 1998

In this paper, we analyze the problems of conventional and previous mehtod on delay test method in IEEE 1149.1. To solve them, we propose two kinds of delay test architectures. One is called ARCH-C, is for combinatonal circuit, and the other is ARCH-S, for clocked sequential circuit. ARCH-C is able to detect delay defect of 0.5 $T_{tck}$ or 1 $T_{tck}$ size. And ARCH-C have a fixed and small amount of hardware overhead, on the contrary preious method has a hardware overhead on the dependent of CUT. This paper discusses weveral problems of Delay test on IEEE 1149.1 for clocked sequential circuit. We suggest the method called ARCH-S, is based on a clock counting technique to generate continuous clocked input of CUT. the simulation results ascertain the accurate operation and effectiveness of the proposed architectures.res.

• Journal of Families and Better Life
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• v.24 no.3 s.81
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• pp.15-25
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• 2006

This study has been performed to identify intelligent ability, reward choice in assumed situation of delay of gratification, and delay of gratification ability. The subjects for this study were 100 preschoolers between the ages of 4 and 5, their mothers, and 15 teachers of three day-care centers in Seoul. T-test, F-test, Correlation analysis and multiple regression analysis were used for data analysis. The main results of this study were as follows: First, preschoolers' delay of gratification ability by mothers' educational background was significant and delay of gratification ability by sex was significant. This means that mothers who had a higher educational background were positively related to preschoolers' delay of gratification ability. Second, in an assumed situation of delay of gratification, preschoolers' delay of gratification ability by reward choice was not significant. Third, delay of gratification by intelligent ability was significant. Fourth, the correlation among intelligent ability, reward choice in assumed situation of delay of gratification and delay of gratification ability were significant. Finally, preschoolers' delay of gratification ability was significantly influenced by two factors: reward choice in assumed situation of delay of gratification and preschoolers' intelligent ability.

• ETRI Journal
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• v.23 no.3
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• pp.138-149
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• 2001

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

• Journal of Preventive Medicine and Public Health
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• v.26 no.4 s.44
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• pp.650-660
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• 1993

This study aims to describe the causes of medically unnecessary hospital stay at a teaching tertiary hospital, using modified version of Delay Tool in which the causes of delay are divided into slx major categories : delay related to test scheduling, test results, surgery, medical staff, patient/family, and administration. For the analysis of hospital stay, 6,479 inpatient-days were reviewed in two medical and four surgical departments for one month. Initially inappropriate hospital stays were identified using Appropriateness Evaluation Protocol (AEP), and causes of delay listed in Delay Tool were assigned to each of them. In both medical and surgical services, the most important cause of delay was related to medical staffs, ranging from 3.6% to 51.6% of total inpatient days. Next important category was delay related to test scheduling in medical services ($4.7{\sim}9.2%$), and delay related to surgery in surgical services ($7.3{\sim}15.0%$). Among subcategories of delay related to medical staffs, delay due to conservative care was the most important cause of inappropriate hospital stay ($2.9{\sim}6.4%$). Each clinical departments had different distribution among delay categories, which could not be fully justified by their clinical charateristics. The Delay Tool would be helpful in exploring factors related to the inefficient use of hospital beds. As a measurement tool of inappropriate hospital stay, however, the Delay Tool should be refined in the definitions of categories and its contents.