• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.1
• /
• pp.41-51
• /
• 2001

In this paper, we presented that the performance of the TCM(Trellis Coded Modulation) using the Euclidean distance is better than that of the convolutional code using the hamming distance under the same bandwidth efficiency. And the TCM DECODER for next generation mobile communication replacing the using convolutional decoder is implemented. Also, for the implementation of the TCM DECODER, the convolutional decoder and the TCM decoder were made by C-language and simulated under AWGN channel with respect to the hard decision and the soft decision. So we proved that performance of the TCM is better than that of the convolutional code. From this result, TCM DECODER, of which constraint length is 3, 5 or 7 and which use the soft decision method, was implemented using the AHDL(Altera Hardware Description Language) and fortified using the Max+plus H version 8.2 of Altera corporation.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.7
• /
• pp.269-277
• /
• 1996

This paper has been presented a design of a POCSAG decoder in RT-level VHDL and implemented in a FPGA chip, and tested. In a single clock of 76.8KHz, the decoder receives all the data of the rate of 512/1200/2400bps and has maximum 2-own frames for service enhancement. To improve decoder performance, the decoder uses a preamble detection cosidering 9% frequency tolerance, a SCW detction and a ICW detection at each 4 bit. The decoder also corrects a address data and a message data up to 2 bits and proposes the PF (preamble frequency) error for saving battery. The decoder increases a battery life owing to turn off RF circuits when the preamble signal is detected with nises. The chip has been designed in RT-level VHdL, synthesized into logic gates using power view$^{TM}$ of viewlogic software. The chip has been implemented in an ALTERA EPF81188GC232-3 FPGA chip with 98% usability, and fully tested in shield room and field room. The chip has been proved that the wrong detection numbers of preamble of noises are significantly reduced in the pager system using PDI 2400 through the real field test. The receiving performance is improved by 20% of aaverage, compared with other existing systems.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.5
• /
• pp.114-124
• /
• 2014

HEVC is a state-of-the-art video coding standard developed by JCT-VC. HEVC provides about 2 times higher subjective coding efficiency than H.264/AVC. One of the main goal of HEVC development is to efficiently coding UHD resolution video so that HEVC is expected to be widely used for coding UHD resolution video. Decoding such high resolution video generates a large number of memory accesses, so a decoding system needs high-bandwidth for memory system and/or internal communication architecture. In order to determine such requirements, this paper presents an analysis of the memory access complexity for HEVC decoder. we first estimate the amount of memory access performed by software HEVC decoder on an embedded system and a desktop computer. Then, we present the memory bandwidth models for HEVC decoder by analyzing the data flow of HEVC decoding tools. Experimental results show the software decoder produce 6.9-40.5 GB/s of DRAM accesses. also, the analysis reveals the hardware decoder requires 2.4 GB/s of DRAM bandwidth.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.96-103
• /
• 2008

This paper proposes a new low-power and small-area Reed-Solomon decoder. The proposed Reed-Solomon decoder using a novel simplified form of the modified Euclid's algorithm can support low-hardware complexity and low-Power consumption for Reed-Solomon decoding. The simplified modified Euclid's algorithm uses new initial conditions and polynomial computations to reduce hardware complexity, and thus, the implemented architecture consisting of 3r basic cells has the lowest hardware complexity compared with existing modified Euclid's and Berlekamp-Massey architectures. The Reed-Solomon decoder has been synthesized using the $0.18{\mu}m$ Samsung standard cell library and operates at 370MHz and its data rate supports up to 2.9Gbps. For the (255, 239, 8) RS code, the gate counts of the simplified modified Euclid's architecture and the whole decoder excluding FIFO memory are only 20,166 and 40,136, respectively. Therefore, the proposed decoder can reduce the total gate count at least 5% compared with the conventional DCME decoder.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.2
• /
• pp.333-340
• /
• 2018

This paper introduces a BCH code decoder using parallel CRC(: Cyclic Redundancy Check) generation. Using a conventional parallel syndrome generator with a LFSR(: Linear Feedback Shift Register), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in $0.35-{\mu}m$ CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.3
• /
• pp.587-594
• /
• 2005

In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.6A
• /
• pp.577-582
• /
• 2008

In this paper, we present a scheme to overcome the worst case complexity of the sphere decoder. If the number of visited nodes reaches the threshold, the detected symbol vector is determined between two candidate symbol vectors. One candidate symbol vector is obtained from the demodulated output of ZF receiver which is initial stage of the sphere decoder. The other candidate symbol vector consists of two sub-symbol vectors. The first sub-symbol vector consists of lately visited nodes running from the most upper layer. The second one contains corresponding demodulated outputs of ZF receiver. Between these two candidate symbol vectors, the one with smaller euclidean distance to the received symbol vector is chosen as detected symbol vector. In addition, we show the upper bound of symbol error rate performance for the sphere decoder using the proposed scheme. In the simulation, the proposed scheme shows the significant reduction of the worst case complexity while having negligible SER performance degradation.

• Korea Multimedia Society
• /
• v.5 no.3
• /
• pp.93-101
• /
• 2001

No Abstract (See Full-text)

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.4A
• /
• pp.546-552
• /
• 2000

The decoding of Turbo-Code relies on the application of a soft input/soft output decoders which can be realized using maximum-a-posteriori(MAP) symbol estimator[l]. Radix-2 MAP decoder can not be used for high speed communications because of a large number of interleaver block size N. This paper proposed a new simple method for radix-4 MAP decoder based on radix-2 MAP decoder in order to reduce the interleave block size. A branch metrics, forward and backward recursive functions are proposed for applying to radix-4 MAP structure with symbol interleaver. Radix-4 MAP decoder shall be illustratively described and its error performance capability shall be compared to conventional radix-2 MAP decoder in AWGN channel.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.4C
• /
• pp.185-190
• /
• 2005

In IS-95 and IMT-2000 systems using variable code rates and constraint lengths, this paper limits code rate 1/2 and constraint length 3 and realizes forward real-time decoder using Sliding-Window with decoding length 6 and PVSL(Prototype Vector Selecting Logic), LVQ(Learning Vector Quantization) in Neural Network. In comparison condition to theoretically constrained AWGN channel environment at $S/(N_{0}/2)=1$ I verified the superiority of forward real-time decoder through hard-decision and soft-decision comparison between Viterbi decoder and forward real-time decoder such as BER and Secure Communication and H/W Structure.