• Title/Summary/Keyword: debugging

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The Design and Implementation of Library for RTOS Q+ (실시간 운영체제 Q+를 위한 라이브러리 설계 및 구현)

  • Kim, Do-Hyeong;Park, Seung-Min
    • The KIPS Transactions:PartD
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    • v.9D no.1
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    • pp.153-160
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    • 2002
  • This paper describes the design and implementation of library for real-time operating system Q+, that was developed for the internet appliance. The library in the real-time operating system should be defined according to the standard interface and support the functions that are adequate to the real-time application. To ensure the compatibility between application programs, the Q+ library follows industrial and international standards, such as POSIX.1, ISO 7942 GKS. And, to support the Q+ application, library provides C standard functions, graphic/window functions, network functions, security support functions, file system functions. The Q+ library was implemented using the Q+ kernel, Digital TV set-top box, and KBUG debugging tool.

The Unified UE Baseband Modem Hardware Platform Architecture for 3GPP Specifications

  • Kwon, Hyun-Il;Kim, Kyung-Ho;Lee, Chung-Yong
    • Journal of Communications and Networks
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    • v.13 no.1
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    • pp.70-76
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    • 2011
  • This paper presents the unified user equipment (UE) baseband modulation and demodulation (modem) hardware platform architecture to support multiple radio access technologies. In particular, this platform selectively supports two systems; one is HEDGE system, which is the combination of third generation partnership project (3GPP) Release 7 high speed packet access evolution (HSPA+) and global system for mobile communication (GSM)/general packet radio service (GPRS)/enhanced data rates for GSM evolution (EDGE), while the other is LEDGE system, which is the combination of 3GPP Release 8 long term evolution (LTE) and GSM/GPRS/EDGE. This is done by applying the flexible pin multiplexing scheme to a hardwired pin mapping process. On the other hand, to provide stable connection, high portability, and high debugging ability, the stacking structure is employed. Here, a layered board architecture grouped by functional classifications is applied instead of the conventional one flatten board. Based on this proposed configuration, we provide a framework for the verification step in wireless cellular communications. Also, modem function/scenario test and inter-operability test with various base station equipments are verified by system requirements and scenarios.

Improvement of a Simulink Debugger Capacity for Model Verification (모델 검사를 위한 Simulink 디버거의 기능 개선)

  • Kim, Seong-Jo;Lee, Hong-Seok;Choi, Kyung-Hee;Chung, Ki-Hyun
    • The KIPS Transactions:PartD
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    • v.17D no.2
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    • pp.111-118
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    • 2010
  • In this paper, we describe the implementation of debugger that has advanced features for verifying Simulink model. The debugger provided in Simulink has some boring and repetitive work when verifying complicated Simulink models or complicated scenarios. In order to resolve the problems, this paper addresses the issues on the implementation of debugger that provides features such as a convenient feature to compare the simulation output to the expected output for specific input, to monitor system's behavior at specific time, and coverage report function in some or all input scenarios. The proposed debugger is applied to the vending machine model provided by Matlab, demonstrating its feasibility.

Design and Implementation of IEEE 802.15.4 Packet Analyzer Based on Embedded Linux (임베디드 리눅스 기반의 IEEE 802.15.4 패킷 분석기 설계 및 구현)

  • Lee, Chang-Woo;Cho, Hyeon-Woo;Ban, Sung-Jun;Kim, Sang-Woo
    • Journal of Institute of Control, Robotics and Systems
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    • v.13 no.12
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    • pp.1173-1178
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    • 2007
  • Ubiquitous sensor network (USN) is composed of many sensor nodes which are one of the simplest form of embedded system. In developing the sensor network system, a debugging tool is necessary to test and verify the system. Recently, a so-called packet analyzer has been developed for this purpose, and it supports IEEE 802.15.4 which is considered as the standard for the sensor network protocols. The major function of the packet analyzer is to take RF packets from sensor nodes and show the structure and the data of the packets graphically to the user. However, the conventional packet analyzers do not support remote control because they require a USB interface along with a personal computer. To make it available for remote control, we propose a new packet analyzer based on a server-client scheme in which a server program is implemented on embedded Linux and a client program is implemented on Windows for convenient use.

An Improving Method of Restructuring Parallel Programs for Data Race Detection

  • Ha, Keum-Sook;Lee, Sung woo;Yoo, Kee-Young
    • Proceedings of the IEEK Conference
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    • 2000.07b
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    • pp.715-718
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    • 2000
  • Although shared memory parallel programs are designed to be deterministic both in their final results and intermediate states, the races that occur when different processes access a common memory location in an order not guaranteed by synchronization could result in unintended non-deterministic executions of the program. So, Detecting races, particularly first data races, is important for debugging explicit shared memory parallel programs. It is possible that all data races reported by other on-the-fly algorithms would disappear once the first races were removed. To detect races parallel programs with nested loops and inter-thread coordination, it must guarantee the order of synchronization operations in an execution instance. In this paper, we propose an improved restructuring method that guarantee ordering execution instance and preserve the semantics of original program. This method requires O(np) time and (s + up) space, where n is the number of total operations, s is the number of synchronization operations and p is the number of parallelism in the execution. Also, this method makes on-the-fly detection of parallel program with nested loops and inter-thread coordination more easily in space and time complexity.

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Virtual ARM Machine for Embedded System Development (임베디드 시스템의 가상 ARM 머신의 개발)

  • Lee, So-Jin;An, Young-Ho;Han, Alex H;Hwang, Young-Si;Chung, Ki-Seok
    • IEMEK Journal of Embedded Systems and Applications
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    • v.3 no.1
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    • pp.19-24
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    • 2008
  • To reduce time-to-market, more and more embedded system developers and system-on-chip designers rely on microprocessor-based design methodology. ARM processor has been a major player in this industry over the last 10 years. However, there are many restrictions on developing embedded software using ARM processor in the early design stage. For those who are not familiar with embedded software development environment or who cannot afford to have an expensive embedded hardware equipment, testing their software on a real ARM hardware platform is a challenging job. To overcome such a problem, we have designed VMA (Virtual ARM Machine), which offers easier testing and debugging environment to ARM based embedded system developers. Major benefits that can be achieved by utilizing a virtual ARM platform are (1) reducing development cost, (2) lowering the entrance barrier for embedded system novices, and (3) making it easier to test and debug embedded software designs. Unlike many other purely software-oriented ARM simulators which are independent of real hardware platforms, VMA is specifically targeted on SYS-Lab 5000 ARM hardware platform, (designed by Libertron, Inc.), which means that VMA imitates behaviors of embedded software as if the software is running on the target embedded hardware as closely as possible. This paper will describe how VMA is designed and how VMA can be used to reduce design time and cost.

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A Dynamic Simulation of Distance Relay Using EMTP MODELS (EMTP MODELS를 이용한 거리 계전기 응동 시뮬레이션)

  • 허정용;김철환;여상민
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.52 no.1
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    • pp.17-28
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    • 2003
  • Digital technology has advanced very significantly over the years both in terms of software tools and hardware available. It is now applied extensively in many area of electrical engineering including protective relaying in power systems. Digital relays based on digital technology have many advantages over the traditional analog relays. The digital relay is able to do what is difficult or impossible in the analog relays. However, the complex algorithms associated with the digital relays are difficult to test and verify in real time on real power systems. Although non real-time simulators like PSCAD/EMTDC are employed to test the algorithms, such simulations have the disadvantage that they cannot test the relay dynamically. Hence, real-time simulators like RTDS are used, but the latter needs large space and it is very expensive. This paper uses EMTP MODELS to simulate the power system and the distance relay. The distance relay algorithm is constructed and the distance relay is interfaced with a test power system. The distance relays performance is then assessed interactively under various fault types, fault distances and fault inception angles. The test results show that we can simulate the distance relay effectively and we can examine the operation of the distance relay very closely including debugging by using EMTP MODELS.

Design of the SD Protocol Analyzer (SD 프로토콜 분석기 설계)

  • Moon, Ji-Hoon;Oh, Jae-Chul
    • The Journal of the Korea institute of electronic communication sciences
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    • v.8 no.11
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    • pp.1697-1706
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    • 2013
  • Protocol analyzer is being used to analyze proper processing of CMD & data when developing SD slave IP. In this thesis, a protocol analyzer was developed for analyzing SD protocol in Windows environment using Visual C++. SD protocol analyzer consists of embedded Linux software for storing SD memory data and MFC program for analyzing this. As for protocol analysis, it has been designed to collect data transmitted from SD memory card to host by Linux software for its analysis by MFC. It was found through the experiment that the CMD type could be confirmed that occurs when reading and writing data to SD memory card using the developed board, and debugging the problems that occur was possible.

Rigorous System Testing by Supporting Vertical Traceability (수직 추적가능성을 제공하는 엄격한 시스템 테스트)

  • Seo, Kwang-Ik;Choi, Eun-Man
    • The KIPS Transactions:PartD
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    • v.14D no.7
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    • pp.753-762
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    • 2007
  • Traceability has been held as an important factor in testing activities as well as model driven development. Vertical traceability affords us opportunities to improve manageability from models and test cases to code in testing and debugging phase. Traceability also makes overcome to difficulties of going up-and-down abstraction level to find out error spot of faults discovered by testing This paper represents a vertical test method which connects a system test level and an integration test level in a test stage by using UML. Experiment of how traceability works and how effective focus on error spots has been included using concrete examples of tracing from models to the code.

Design of Monitoring System for efficient debugging on Embedded Environment (임베디드 환경에서의 효율적인 디버깅을 위한 모니터링 시스템 설계)

  • Shin Won;Kim Tae Wan;Chang Chun Hyon
    • Proceedings of the Korea Information Processing Society Conference
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    • 2004.11a
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    • pp.615-618
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    • 2004
  • 최근 가정 혹은 사무실과 같은 장소에서 DVD 플레이어. 셋탑박스, MP3 플레이어 등 많은 임베디드 시스템들을 볼 수 있다. 임베디드 시스템(embedded system)이 점점 많은 분야에서 사용됨에 따라 시스템 운영을 위한 임베디드 소프트웨어들도 각 분야에 맞는 다양한 구조와 기능들이 필요하다. 하지만, 한정된 시간에 다양한 구조와 기능들을 구현해야 하는 소프트웨어 개발은 큰 어려움이 따른다. 이러한 소프트웨어 개발을 좀 더 빠르고 쉽게 하기 위해 프로파일링, 디버거 등의 도구들이 등장했다. 그 중 디버거는 개발 기간 단축을 위한 필수적인 도구이다. 기존의 디버거는 모든 변수에 대한 모니터링으로 생기는 오버헤드와 디버거 모듈을 삽입함으로써 많은 자원을 소비하는 문제가 발생한다. 한정된 자원을 사용하는 임베디드 시스템에서의 불필요한 자원소비와 복잡한 처리 등은 프로그램 강제 종료, 시스템 오작동 등의 큰 문제를 발생시키는 요인이 된다. 본 논문에서는 이와 같은 문제 해결을 위해 사용자가 원하는 변수만을 모니터링 하여 자원소모를 최소화할 수 있는 모니터링 센서 기법과 실행시간 중에 모니터링 대상을 변경하여 빠른 디버깅을 지원 하는 디버깅 레벨 기법을 제안한다.

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