• Journal of Institute of Control, Robotics and Systems
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• v.20 no.4
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• pp.474-479
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• 2014

LEON3 is a 32-bit synthesizable processor based on the SPARC V8. It can be connected to AMBA 2.0 bus and has a 7- stage pipeline, IEEE-754 FPU and 256[KB] cache. It can be easily implemented using FPGA and used for a SoC design. DSU which comes with LEON3 can be used to control and monitor the operation of LEON3. And DSU makes it easy to set a debugging environment for the development of both hardware and software for an embedded systems based on LEON3. This paper presents the summary of the debugging tool for LEON3 based embedded systems. The debugging tool can initialize the target hardware, find out how the target hardware is configured, load application code to a specified memory space and run that application code. To provide users a debugging environment, it can set breakpoints and control the operation of LEON3 correspondingly. And function call trace is one of key functions of the debugging tool.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.24-38
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• 2009

In this paper, we implement processor debugger based on OCD(On-Chip Debugger). Implemented debugger consist of software debugger that supports a functionality of symbolic debugging, OCD integrated into target processor as a function of debugging, and Interface & Control block which interfaces software debugger and OCD at high speed rates. The debugger supports c/assembly level debugging using software debugger as OCD is integrated into target processor. After OCD block is interfaced with 32bit RISC processor core and then implemented with FPGA, the verification of On-Chip Debugging System is carried out through connecting OCD and Interface & Control block, and SW debugger.

• Journal of the Korea Society for Simulation
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• v.15 no.4
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• pp.51-58
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• 2006

Debugging embedded softwares is very different from debugging general softwares. For examples, debugging embedded software requires more information, such as information on power consumption, information on the distribution of executed instructions, information on the distribution of used registers, and information on the amount of clocks consumed during the execution of a program, that is not needed in debugging general softwares. In this paper, we propose more effective method fer debugging embedded softwares using an instruction set simulator for the microprocessor that is executing embedded softwares. In this research, we develop a debugger based on an instruction set simulator for a domestic embedded microprocessor called SE1608 and we shows an effective debugging method using a MiBench program which is widely used to benchmark embedded softwares. The debugging method proposed in this paper is relatively easy to implement and shows many advantages compared with existing debugging methods.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.170-176
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• 2002

Java language is a representative object-oriented language that is used at the various platform and fields. A structure of java language is simpler than traditional procedural-oriented language because of characters of object-oriented language But it is difficult to debug complicated java programs. Debugging has always been a costly part of software development. Syntax errors of java programs is easily found by the current debugging system. But it is difficult to locate logical errors included in java programs. Traditional debugging techniques locating logical errors in java program have been still used with conventional methods that are used at procedural-oriented languages. Unfortunately, these traditional methods are often inadequate for the task of isolating specific program errors. Debugger users may spend considerable time debugging code of program development with sequential methods according as program size is large and is complicated. It is important to easily locate errors included in java program in the software development. In this paper, we apply algorithmic debugging method that debugger user can easily debug programs to java program. This method executes a program and makes an execution tree from calling relation of functions. And it locates errors at the execution tree. So, Algorithmic debugging method can reduce the number of debugging than conventional sequential method.

• Proceedings of the IEEK Conference
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• summer
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• pp.61-65
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• 2004

An on-chip debugging unit is proposed aiming performance enhancement of JTAG-based SoC systems. The proposed unit comprises a JTAG module and a core breaker. The IEEE 1149.1 standard has been modified and applied to the new JTAG module. The proposed unit eliminates redundant clock cycles included in the TAP command execution stage reducing overall debugging time. TAP execution commands are repeatedly issued to perform debugging of complicated SoC systems. Simulation on the proposed unit shows some $14\%$ performance enhancement and $50\%$ gate count reduction compared to the conventional ones.

• The KIPS Transactions:PartD
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• v.9D no.4
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• pp.659-666
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• 2002

Park, Seo and Kim (12) developed the input domain-based SRGM, which was able to quantitatively assess the reliability of a software system during the testing and operational phases. They assumed perfect debugging during testing and debugging phase. To make this input domain-based SRGM more realistic, this assumption should be relaxed. In this paper we generalize the input domain-based SRGM under imperfect debugging. Then its statistical characteristics are investigated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.84-92
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• 2002

As today's field programmable gate arrays have very large logic capacity as well as relatively fast operation speed, they're widely used in many application areas. However, debugging the design implemented in FPGA's is very time-consuming and painful as the internal signal probing usually requires large number of FPGA re-compilations, which take tremendously long time. In this paper, we analyze the problems in FPGA debugging and propose a new powerful debugging solution. With the proposed FPGA debugging solution, we can guarantee not only to provide 100% internal signal visibility without FPGA re-compilation for the design in FPGA's, but also to identify at least one design bug per FPGA compilation. An experimental result has clearly shown the proposed approach to FPGA debugging very powerful and practical.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.305-312
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• 2003

In the embedded Linux environments, developers can concurrently debug multiple processes that have parent-child relationships using multiple gdbs and gdbservers. But, it needs additional coding efforts and messy works of activating another gdbs and gdbservers for each created process, and so, it may be inefficient in the viewpoint of developers. In this paper, we propose a mgdb library and mgdbserver that supports concurrent debugging of multiple processes in the embedded Linux systems by using the library wrapping mechanism without modifying the kernel. Also, through the experimentation of concurrent debugging for multiple processes that communicate by an unnamed pipe, we show that our proposed debugging mechanism is more efficient than the preexisting mechanisms.

• ETRI Journal
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• v.35 no.2
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• pp.301-310
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• 2013

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.

• Journal of Information Processing Systems
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• v.6 no.4
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• pp.537-552
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• 2010

Software Debugging is the most time consuming and costly process in the software development process. Many techniques have been proposed to isolate different faults in a program thereby creating separate sets of failing program statements. Debugging in parallel is a technique which proposes distribution of a single faulty program segment into many fault focused program slices to be debugged simultaneously by multiple debuggers. In this paper we propose a new technique called Faulty Slice Distribution (FSD) to make parallel debugging more efficient by measuring the time and labor associated with a slice. Using this measure we then distribute these faulty slices evenly among debuggers. For this we propose an algorithm that estimates an optimized group of faulty slices using as a parameter the priority assigned to each slice as computed by value of their complexity. This helps in the efficient merging of two or more slices for distribution among debuggers so that debugging can be performed in parallel. To validate the effectiveness of this proposed technique we explain the process using example.