• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.953-956
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• 2000

Application specific DSPs often employ irregular datapath structures with distributed registers. In the scheduling phase of retargetable compilation, resolution of register usage conflicts comes to be a new constraint for such datapaths. This paper presents a method of register constraint analysis which attempts to minimize the number of the spill codes required for resolving the register usage conflicts. It searches for a set of ordering restrictions among operations which sequentialize the lifetimes of the values residing in the same register as much as possible and thus minimize the number of the register conflict. Experimental results show that a combination of the proposed register constraint, analysis and list-based scheduling reduces the number of the register spills into 25%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.454-468
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• 1997

This paper presents a bitwidth optimization algorithm for efficient hardware sharing in digital signal processing system. The proposed algorithm determines the fixed-point representation for each signal through bitwidth optimization to generate the hardware requiring less area. To reduce the operator area, the algorithm partitions the abstract operations in the design description into several groups, such that the operations in the same group can share an operator. The partitioning result are fed to a high-level synthesis system to generate the pipelined fixed-point datapaths. The proposed algorithm has been implemented in SODAS-DSP an automatic synthesis system for fixed-point DSP hardware. Accepting the models of DSP algorithms in schematics, the system automatically generates the fixed-point datapath and controller satisfying the design constraints in area, speed, and SNR(Signal-to-Noise Ratio). Experimental results show that the efficiency of the proposed algorithm by generates the area-efficient DSP hardwares satisfying performance constraints.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.491-494
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• 2008

과거 CDMA 시스템에서 이동단말과 PSTN 및 PSDN간의 통신이 가능하게 하기 위해서는 망간의 정합기능을 수행하는 연동장치(IWF Inter-Working Function)가 필요로 되는데, 이때 이동단말과 BSC/MSC간의 무선 데이터를 IWF로 HDLC 프레임 형태로 구동하고 반대로 IWF로부터 수신된 데이터 프레임을 이동 단말측으로 전달하기 위하여 HDLC frame driver의 역할이 필요하다. 또한 교환기와 IWF간의 데이터 통신은 Frame-relay 프로토콜을 이용하며 정합기능을 수행해 주어야 한다. 본 논문에서 구현된 기능은 과거 CDMA 의 MSC 내에 구현된 본 기능이 HDLC 정합, Frame-Relay 정합, IPC, Datapath 등의 기능들로 구분되어 분리되어 있는 구조를 통합하여 하나의 기능 Board로 통합하였고 이러한 기능을 MG(Media Gateway) System에 기반하여 구현하여 적용하였다.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.773-776
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• 2003

This paper presents new hardware implementation of the ECC(Elliptic Curve Cryptography) algorithm that is improved in speed and stability. We proposed new datapath that changed square's position so that we can reduce required number of cycles for addition operation between two points by more than 30%. We used Massey-Omura parallel multiplier adopted Normal basis for fast scalar multiplications. Also the use of the window non-adjacent form (WNAF) method can reduce addition operation of each other different points. We implemented ECC system with GF($2^{196}$), and this system was designed and verified by VHDL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.164-166
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• 2016

PRESENT/ARIA/AES의 3가지 블록 암호 알고리즘을 지원하는 암호 프로세서를 MPW(Multi-Project Wafer)칩으로 구현하였다. 설계된 블록 암호 칩은 PRmo(PRESENT with mode of operation) 코어, AR_AS(ARIA_AES) 코어, AES-16b 코어로 구성된다. PRmo는 80/128-비트 마스터키와, ECB, CBC, OFB, CTR의 4가지 운영모드를 지원한다. 128/256-비트 마스터키를 사용하는 AR_AS 코어는 서로 내부 구조가 유사한 ARIA와 AES를 통합하여 설계하였다. AES-16b는 128-비트 마스터키를 지원하고, 16-비트 datapath를 채택하여 저면적으로 구현하였다. 설계된 암호 프로세서를 FPGA검증을 통하여 정상 동작함을 확인하였고, 0.18um 표준 셀 라이브러리로 논리 합성한 결과, 100 KHz에서 52,000 GE로 구현이 되었으며, 최대 92 MHz에서 동작이 가능하다. 합성된 다중 암호 프로세서는 MPW 칩으로 제작될 예정이다.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.7
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• pp.359-367
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• 2005

This paper presents a scheduling approach for synthesizing pipelined datapaths under resource constraints. The proposed approach evaluates whether or not a scheduling solution can exist in case an operation temporarily is assigned to the earliest or latest control step among the assignable steps for the operation. If a solution cannot be found, it is impossible to assign the operation to that control step due to a violation against resource constraints, and so we can eliminate that control step among candidate assignable control steps. The proposed algorithm builds up a schedule based on gradual mobility reduction and finds a solution that yields high performance by evaluating on the impact on register assignment. Experiments on benchmarks show that this approach gains a considerable improvement over previous approaches.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.470-476
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• 2000

This paper describes an IP design of a low-power microcontroller using an architecture level design methodology instead of a transistor level. To reduce switching capacitance, the register-toregister data transfer is adopted to frequently used register transfer micro-operations. Also, distributed buffers are proposed to reduce a input data rising edge time. To reduce power consumption without any loss of performance, pipeline processing should be used. In this paper, a 4-stage pipelined datapath being able to process CISC instructions is designed. Designed microcontroller lessens power consumption by 20%. To measure a power consumption, the SYNOPSYS EPIC powermill is used.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.485-487
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• 2017

The whirlpool hash function adopted as an ISO / IEC standard 10118-3 by the international standardization organization is an algorithm that provides message integrity based on an SPN (Substitution Permutation Network) structure similar to AES block cipher. In this paper, we describe the hardware implementation of the Whirlpool hash function. The round block is designed with a 64-bit data path and encryption is performed over 10 rounds. To minimize area, key expansion and encryption algorithms use the same hardware. The Whirlpool hash function was modeled using Verilog HDL, and simulation was performed with ModelSim to verify normal operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2333-2340
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• 2016

A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.

• Journal of IKEEE
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• v.23 no.4
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• pp.1321-1327
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• 2019

This paper describes an efficient hardware implementation of modular square root (MSQR) computation over GF(p), which is the operation needed to map plaintext messages to points on elliptic curves for elliptic curve (EC)-ElGamal public-key encryption. Our method supports five sizes of elliptic curves over GF(p) defined by the National Institute of Standards and Technology (NIST) standard. For the Koblitz curves and the pseudorandom curves with 192-bit, 256-bit, 384-bit and 521-bit, the Euler's Criterion based on the characteristic of the modulo values was applied. For the elliptic curves with 224-bit, the Tonelli-Shanks algorithm was simplified and applied to compute MSQR. The proposed method was implemented using the finite field arithmetic circuit with 32-bit datapath and memory block of elliptic curve cryptography (ECC) processor, and its hardware operation was verified by implementing it on the Virtex-5 field programmable gate array (FPGA) device. When the implemented circuit operates with a 50 MHz clock, the computation of MSQR takes about 18 ms for 224-bit pseudorandom curves and about 4 ms for 256-bit Koblitz curves.