• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.10 no.4
• /
• pp.175-183
• /
• 1985

Dataflow computers exhibit a high degree of parallelism which can not be obtained easily with the conventional von-Neumann architecture. Since many instructions are ready for execution simultaneously, concurrency can be easily achieved by the multiple processors modified the dataflow machine. This paper describes a FFT Butterfly algorithm for dataflow computation and evaluates the performance by the speed up factor of that algorithm through the simulation approach by the time-accelation method.

• Journal of KIISE:Computing Practices and Letters
• /
• v.15 no.4
• /
• pp.231-243
• /
• 2009

Many DSP systems are streaming applications in which streams of data constantly flow through a set of filters. Dataflow programming paradigm is one of effective methods for representing these streaming applications. Dataflow programming model explicitly exposes parallelisms within an application, which helps compiling of the application onto a multicore platform. We propose SPEX(Signal Processing Extension), a language extension to a standard imperative language based on the parameterized dataflow model. Parameterized dataflow model is a kind of dataflow model that can express a modest fashion of dynamism contrary to the synchronous dataflow that can represent only static dataflow. SPEX facilitates characterizing an application written in conventional imperative languages such C/C++ as a streaming application. SPEX is comprised of a few keywords augmented to the conventional C++ syntax for representing dataflow paradigm. SPEX also restricts the syntax and semantics of C++ in order to fit the program within a certain streaming programming category. In this paper, we focus on the capability of SPEX in representing streaming computations within filters and streaming communications among filters.

• 제어로봇시스템학회:학술대회논문집
• /
• 1991.10a
• /
• pp.1110-1115
• /
• 1991

Tne mathematical modeling and analysis results of a dataflow logic solving processor(DFLSP) for programmable logic controller(PLC) are proposed in this paper. The logic program language is formalized using a dataflow graph model. From this dataflow graph, the instruction precedence relationship, and deadlock problems, which are major properties of a logic program, are described.

• Proceedings of the KIEE Conference
• /
• 1991.07a
• /
• pp.877-880
• /
• 1991

In this paper, the architecture of a dataflow logic solving processor for programmable logic controller is proposed. As the proposed DFLSP(dataflow logic solving processor) is designed based on the dataflow architecture, it has inherently concurrent processing and data synchronization capabilities. And also, it has dynamic load balancing capabilites which increases the utilization of the whole system that can he hardly implemented in other multiprocessor system. The re-matching unit gets rid of unnecessary matching cycles in LSU, which increases the performance of LSU and allows the multiple input multiple output operations.

• 제어로봇시스템학회:학술대회논문집
• /
• 1990.10a
• /
• pp.634-638
• /
• 1990

In this paper, the architecture of a dataflow logic solving processor for programmable logic controller is proposed. As the proposed DFLSP (dataflow logic solving processor) is designed based on the dataflow architecture, it has inherently concurrent processing and data synchronization capabilities. The proposed DFLSP is adequate for high speed programmable logic controllers and gets rid of data synchronization problem in hardware level. The performance of the proposed DFLSP is analyzed using computer simulations and prototype hardware. With single processing element, the logic solving time is 144 usec per 1K steps of logic program and with eight processing elements, the logic solving time is 23 usec per 1K steps of logic program with reasonable assumptions.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.2
• /
• pp.225-235
• /
• 1986

Dataflow computers exhibit a high degree of parallelism which can not be obtained easily with the conventional von-Neumann architecture. Since many instructions are ready for execution simultaneously, concurrency can easily by achieved by the multiple processors modified the data-flow machine. In paper, we describe an improved dataflow architecture which is designed by adding the demand propagation network to the MIT dataflow machine. and show the improved performance by the execution time and the efficiency of processing elements through simulation with the time acceleration method.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.9
• /
• pp.2435-2446
• /
• 1998

In this paper. We describe a dataflow model for efficient execution of a functional logic language and a method of translation a functional logic language into a dataflow graph. To explore parallelism and intelligent backtracking, we us model in which clause and function are represented as independent dataflow graph. The node denotes basic actions to be performed when the clause and function are executed. The dataflow mechanism allows an operation to be executed as soon as all its operands are available. Since the operations can never be executed earlier, a dataflow model is an excellent base for increasing execution speed. We did decrease a delay time with concurrent execution of dependency analysis and subgoal.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2024.05a
• /
• pp.723-726
• /
• 2024

단일 dataflow 를 지원하는 DNN 가속기는 자원 효율적인 성능을 보이지만, 여러 DNN 모델에 대해서 가속 효과가 제한적입니다. 반면에 모든 dataflow 를 지원하여 매 레이어마다 최적의 dataflow를 사용하여 가속하는 reconfigurable dataflow accelerator (RDA)는 굉장한 가속 효과를 보이지만 여러 dataflow 를 지원하는 과정에서 필요한 추가 하드웨어로 인하여 효율적이지 못합니다. 따라서 본 연구는 제한된 dataflow 만을 지원하여 추가 하드웨어 요구사항을 감소시키고, 중복되는 하드웨어의 재사용을 통해 최적화하는 새로운 가속기 설계를 제안합니다. 이 방식은 자원적 한계가 뚜렷한 엣지 디바이스에 RDA 방식을 적용하는데 필수적이며, 기존 RDA 의 단점을 최소화하여 성능과 자원 효율성의 최적점을 달성합니다. 실험 결과, 제안된 가속기는 기존 RDA 대비 32% 더 높은 에너지 효율을 보이며, latency 는 불과 1%의 차이를 보였습니다.

• Journal of the Korea Society of Computer and Information
• /
• v.7 no.2
• /
• pp.19-33
• /
• 2002

In this Paper, we described the Parwan CPU using a VHDL at the behavioral level and then described by connecting CPU components at the dataflow level. Finally, we simulated to verify of execution of a CPU processor using a test-bench method. A presented design method was to enable information exchange of design and representation of operation were very exact and simple. Also. a documentation of design was available and it was easy that verify a operation of designed processor. The behavioral description of VHDL aids designer as we verify our understanding of the designed system, while the dataflow description can be used to verify the bussing and register structure of the design.

• Journal of the Korea Computer Industry Society
• /
• v.9 no.4
• /
• pp.157-170
• /
• 2008

In this paper, we described the Parwan(PAR-1) CPU that be developed as a reduced processor at Messachusetts Microelectronics Center using a VHDL at the behavioral level and then described by connecting CPU components at the dataflow level. Finally, we used Test-bench method to simulate and verify execution of CPU processor that was designed using a VHDL <중략> Here, Presented method was to enable information exchange of design and representation of operation were very exact and simple. Also, a documentation of design was available and it was easy that verify a operation of designed processor. The behavioral description of VHDL aids designer as we verify our understanding of the designed system, thus the dataflow description can be used to verify the bussing and register structure of the design.