• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.769-770
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• 2008

Mani Memory DataBase(MMDB) system store their data in main physical memory and provide very high-speed access. Conventional database system are optimized for the particular characteristics of disk storage mechanism. Memory resident systems, on the other hand, use different optimizations to structure and organize data, as well as to make it reliable. This paper provides a brief overview on MMDBs and the results after evaluating the performance of our simple MMDB based on Embedded system.

• 정보와 통신
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• 제25권12호
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• 대한임베디드공학회논문지
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• 제14권2호
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• pp.79-86
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• 2019

For decades, in-memory data structures have been designed for DRAM-based main memory that provides symmetric read/write performances and has no limited write endurance. However, such data structures provide sub-optimal performance for NVM as it has different characteristics to DRAM. With this motivation, we rethink a conventional red-black tree in terms of its efficacy under NVM settings. The original red-black tree constantly rebalances sub-trees so as to export fast access time over dataset, but it inevitably increases the write traffic, adversely affecting the performance for NVM with a long write latency and limited endurance. To resolve this problem, we present a variant of the red-black tree called a hierarchical balanced binary search tree. The proposed structure maintains multiple keys in a single node so as to amortize the rebalancing cost. The performance study reveals that the proposed hierarchical binary search tree effectively reduces the write traffic by effectively reaping the high capacity of NVM.

• Journal of Internet Technology
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• 제21권3호
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• pp.849-859
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• 2020

High-performance computing (HPC) systems provide huge computational resources and large memories. The hybrid memory is a promising memory technology that contains different types of memory devices, which have different characteristics regarding access time, retention time, and capacity. However, the increasing performance and employing hybrid memories induce more complexity as well. In this paper, we propose a roofline-based data migration methodology called HyDM to effectively use hybrid memories targeting at Intel Knight Landing (KNL) processor. HyDM monitors status of applications running on a system and migrates pages of selected applications to the High Bandwidth Memory (HBM). To select appropriate applications on system runtime, we adopt the roofline performance model, a visually intuitive method. HyDM also employs a feedback mechanism to change the target application dynamically. Experimental results show that our HyDM improves over the baseline execution the execution time by up to 44%.

• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1989년도 춘계학술대회
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• pp.39-43
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• 1989

In this paper, hierachical representation method with a 1-to-4 and 1-to-8 data structure is used to reconstruct the three-dimensional scene from two-dimensional cross sections provided by computed tomography with small memory computer system. To reduce the internal memory use, 2-D section is represented by quadtree, and 3-D scene is represented by octree. Octree is constructed by recursively merging consecutive quadtrees. This method uses 7/200 less memory than pointer type structure with all the case, and less memory up to 60.3% than linear octree with experimental data.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• 대한임베디드공학회논문지
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• 제17권1호
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• pp.59-65
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• 2022

Virtual memory is used as the method to ensure the safety of the system through memory protection in the real-time system. TLB miss caused by using virtual memory makes the real-time system WCET more pessimistically. TLB lockdown can be applied as a method to improve this problem. However, processors with limited TLB lockdown entries, a selection criterion is needed to efficiently utilize the TLB lockdown entry. In this paper, the most frequently accessed virtual pages in the process are applied to the TLB lockdown by analyzing memory profiling. The results showed that micro data TLB miss stall cycle and main data TLB miss stall cycle of the processor decreased by at least 4.7% and up to 29.7%.

• Journal of Information Technology Applications and Management
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• 제11권2호
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• pp.29-43
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• 2004

As the development of an information technique, gradually, mobile device is going to be miniaturized and operates at high speed. By such the requirements, the devices using a flash memory as a storage media are increasing. The flash memory consumes low power, is a small size, and has a fast access time like the main memory. But the flash memory must erase for recording and the erase cycle is limited. JFFS is a representative filesystem which reflects the characteristics of the flash memory. JFFS to be consisted of LSF structure, writes new data to the flash memory in sequential, which is not related to a file size. Mounting a filesystem or an error recovery is achieved through the sequential approach. Therefore, the mounting delay time is happened according to the file system size. This paper proposes a MJFFS to use a multi-checkpoint information to manage a mass flash file system efficiently. A MJFFS, which improves JFFS, divides a flash memory into the block for suitable to the block device, and stores file information of a checkpoint structure at fixed interval. Therefore mounting and error recovery processing reduce efficiently a number of filesystem access by collecting a smaller checkpoint information than capacity of actual files. A MJFFS will be suitable to a mobile device owing to accomplish fast mounting and error recovery using advantage of log foundation filesystem and overcoming defect of JFFS.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권2호
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• pp.467-479
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• 2022

Working memory (WM), which plays a vital role in daily activities, is a memory system that temporarily stores and processes information when people are engaged in complex cognitive activities. The influence of music on WM has been widely studied. In this work, we conducted a series of n-back memory experiments with different task difficulties and multiple trials on 14 subjects under the condition of no music and Alpha wave leading music. The analysis of behavioral data show that the change of music condition has significant effect on the accuracy and time of memory reaction (p<0.01), both of which are improved after the stimulation of Alpha wave music. Behavioral results also suggest that short-term training has no significant impact on working memory. In the further analysis of electrophysiology (EEG) data recorded in the experiment, auto-regressive (AR) model is employed to extract features, after which an average classification accuracy of 82.9% is achieved with support vector machine (SVM) classifier in distinguishing between before and after WM enhancement. The above findings indicate that Alpha wave leading music can improve WM, and the combination of AR model and SVM classifier is effective in detecting the brain activity changes resulting from music stimulation.

• 대한전자공학회논문지SD
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• 제44권1호
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• pp.45-50
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• 2007

본 논문에서는 상변환 메모리 (phase-change random access memory: PRAM)의 저전력 선택적 데이터 쓰기(selective data write: SDW) 기법을 제안하였다. PRAM은 쓰기 동작 과정에서 큰 전류를 오랜 시간동안 소모하기 때문에 큰 쓰기 전력을 소모한다. 이 쓰기 전력을 줄이기 위하여, SDW 기법은 쓰기 동작 과정에서 PRAM 셀에 데이터를 쓰기 전에 우선 저장될 셀의 데이터를 읽어온다. 셀의 기존 데이터와 새롭게 저장할 데이터를 비교하여, 입력된 데이터와 저장된 데이터가 다른 경우에만 PRAM 셀에 데이터 쓰기를 수행한다. 제안된 쓰기 기법을 사용하여 전력 소모를 반 이상으로 줄일 수 있다. 1Kbits ($128{\times}8bits$) PRAM 테스트 칩을 $0.5{\mu}m$ GST 셀과 $0.8{\mu}m$ CMOS 공정을 사용하여 구현하였다.