• Korean Journal of Optics and Photonics
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• v.17 no.1
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• pp.68-74
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• 2006

We have extracted an optical clock signal from a return-to-zero(RZ) pseudorandom bit sequence(PRBS) and non-return-to-zero(NRZ) PRBS data in a pulsation multi-section laser diode with DFB reflector. The ms timing jitter achieved less than 1 ps for the input 11.727 Gbit/s RZ PRBS and NRZ PRBS data. The PRE data wasconverted from the NRZ data using an NRZ to pseudo-return to zero(PRZ) converter module. The optical clock was extracted from the PRZ data which contains the clock components. Although the input PRZ data gives a timing jitter of 2 ps, the extracted clock has timing jitter of ${\~}$1 ps.

• Journal of the Korea Society of Computer and Information
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• v.26 no.11
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• pp.139-147
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• 2021

BIBFRAME, which is attracting attention as an alternative to the machine-readable catalog format (MARC) in the library world, presents a new bibliographic data model in the open web environment while maintaining compatibility with existing data. To convert KORMARC(Korean data model of MARC) records into BIBFRAME, we extract 25 key fields by analyzing the latest 5,000 bibliographic data from Nowon-gu Library in Seoul. The extracted core fields are classified into three types according to the compatibility of MARC 21, and define conversion rules for each type. In addition, implement an open source-based converter to perform KORMARC to BIBFRAME conversion. As a basic study on KORMARC to BIBFRAME conversion, this study is meaningful in that it analyzes the latest KORMARC information actually used, defines conversion rules, and attempts BIBFRAME conversion.

• Journal of the Optical Society of Korea
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• v.19 no.4
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• pp.334-339
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• 2015

Terabit-per-second (Tb/s) transmission capacity for the next generation of long-haul communication networks can be achieved using multicarrier optical super-channel technology. In an elastic orthogonal frequency division multiplexing (OFDM) super-channel transmission system, demultiplexing a portion of an entire spectrum in the form of a subband with minimum power is critically required. A major obstacle to achieving this goal is the analog-to-digital converter (ADC), which is power-hungry and extremely expensive. Without a proper ADC that can work with low power, it is unrealistic to design a 100G coherent receiver suitable for a commercially deployable optical network. Discrete Fourier transform (DFT) is often seen as a primary technique for understanding partial demultiplexing, which can be attained either optically or electronically. If fairly comparable performance can be achieved with an all-optical DFT circuit, then a solution independent of data rate and modulation format can be obtained. In this paper, we investigate two distinct OFDM super-channel receiver models, based on electronic and all-optical DFT-technologies, for partial carrier demultiplexing in a multi-Tb/s transmission system. The performance comparison of the receivers is discussed in terms of bit-error-rate (BER) performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.317-322
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• 2015

Recently, due to the variety and complexity of marine electronics communication devices, much research has been done to adopt the novel communication protocol. Among them, NMEA2000 protocol, is adopted as standardized protocol to the next generation ship. In this paper, we design and implement the conversion algorithm for sensor protocol based on NMEA2000, and analog data module which convert data format between NMEA2000, CAN, Ethernet, RS232. The present study was designed to implement user-based data monitoring system by supporting various communication protocols through the development and application of key technologies through NMEA2000.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.332-346
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• 2003

In this paper, a system which can compress and reconstruct the digital image was implemented using 2 dimensional DWT(Discrete Wavelet Transform). The proposed system consists of the FPGA board tocompress the image and the application software(S/W) to reconstruct it. First the FPGA receives the image from AID converter and compresses the image using wavelet transform. The compressed data is transferred into the PC using the PCI interface. The compressed image is reconstructed by an application S/W inside the PC. The image compressor can compress about 60 fields per second, in which the image format was NTSC YCbCr(4:2:2) and the image size was 640${\times}$240 pixels per field. The designed hardware mapped into one FPGA occupying 11,120 LAB (Logic Array Block) and 27,456 ESB(Embedded System Block) in APEX20KC EP20K1000B652-7. It globally uses 33MHz clock and the memory control part uses 100MHz.