• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.3
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• pp.7-12
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• 2016

DRAM is commonly used as a smartphone memory medium, but extending its capacity is challenging due to DRAM's large battery consumption and density limit. Meanwhile, smartphone applications such as social network services need increasingly large memory, resulting in long latency due to additional storage accesses. To alleviate this situation, we adopt emerging nonvolatile memory (NVRAM) as smartphone's buffer cache and propose an efficient management scheme. The proposed scheme stores all dirty data in NVRAM, thereby reducing the number of storage accesses. Moreover, it separately exploits read and write histories of data accesses, leading to more efficient management of volatile and nonvolatile buffer caches, respectively. Trace-driven simulations show that the proposed scheme improves I/O performances significantly.

• Journal of Korean Society for Geospatial Information Science
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• v.17 no.1
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• pp.167-174
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• 2009

A Tile Map Service is a regular map service that has been enhanced to serve maps very quickly using a cache of static images. The map cache is a directory that contains image tiles of a map extent at specific scale levels. Returning a tile from the cache takes the server much less time than drawing the map image on demand. Use of a Tile Map Service can dramatically improve the time that clients take to display complex base-maps. Using Tile Map Services thus eliminate the need to trade quality for performance. This study provides a way to construct Tile Map Service System using Open Source GIS. We used GDAL(Geospatial Data Abstraction Library) which is one of the Open Source GIS Softwares to make Tile Map Image and OpenLayers to publish Web Page. Moreover, We conducted a performance test on Tile Map System and Dynamic Map System and evaluated the results of it. As a result, the proposed method makes it easier to construct high performance Tile Map Service using Open Source GIS without commercial products.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.447-454
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• 2001

Various caching and prefetching algorithms have been investigated to identify and effective method for improving the performance of I/O devices. A prefetching algorithm decreases the processing time of a system by reducing the number of disk accesses when an I/O is needed. This paper proposes an AMBA prefetching method that is an extended version of the OBA prefetching method. The AMBA prefetching method will prefetching blocks continuously as long as disk bandwidth is enough. In this method, though there were excessive data request rate, we would expect efficient prefetching. And in the AMBA prefetching method, to prevent the cache pollution, it limits the number of data blocks to be prefetched within the cache area. It can be implemented in a user-level File System based on a Linux Operating System. In particular, the proposed prefetching policy improves the system performance by about 30∼40% for large files that are accessed sequentially.

• Journal of Digital Convergence
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• v.15 no.8
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• pp.341-349
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• 2017

CCN proposes that intermediate network nodes on a network path for a transmitted data-packet cache the data-packet. If the nodes receive request packets for the cached data, the nodes can directly respond to the request-packets using the cached data. Since a request-packet can be responded by one of the intermediate nodes on a path of the request-packet, both faster response time and decreased data transmission amount are expected comparing to the existing host centric networking. However, CCN is vulnerable against forgery attacks because data-packet receivers cannot identify a data provider. Hence, a data authentication scheme is essentially needed to make CCN more secure. But such a data authentication process is one of the main causes of CCN-based service delays. This paper first analyzes the problems of a CCN data authentication scheme, then proposes an improved authentication operation scheme for efficiently authenticating data, and finally evaluates its performance.

• Journal of Industrial Technology
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• v.21 no.A
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• pp.73-80
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• 2001

Barrier is widely used for synchronization in parallel programs. Since the process arrived earlier than others should wait at the barrier, the total processor utilization decreases. In this paper, to find the sources of the barrier waiting time, parallel programs are executed on the various grain sizes through execution-driven simulations. In simulation studies, we found that even if approximately equal amounts of work are distributed to each processor, all processes may not arrive at a barrier at the same time. The reasons are that the different numbers of cache misses and instructions within partitioned grains result in the difference in arrival time of processors at the barrier.

• Proceedings of the Korean Society of Computer Information Conference
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• 2017.01a
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• pp.143-144
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• 2017

최근 그래픽 처리 장치는 DRAM에 대한 접근을 줄이고자 여러 메모리 계층을 사용하고 있다. GPGPU의 L2 캐쉬는 요청 데이터의 타입에 따라 별도로 접근하는 L1 메모리와 다르게 레이턴시가 긴 DRAM에 접근하기 전에 모든 데이터 타입이 접근 가능한 캐쉬이다. 본 논문에서는 애플리케이션에서 명시하는 다양한 데이터 타입에 대하여 접근 및 적재를 허용하는 L2 캐쉬를 오직 텍스쳐 데이터만을 허용하도록 하여 변화하는 성능을 분석하고자 한다. 본 실험을 위해 텍스쳐 데이터 이외의 데이터 타입은 L2 캐쉬를 바이패스하여 바로 DRAM에 접근하도록 구조를 변경한다. 실험을 통한 분석 결과 텍스쳐 데이터만을 허용하는 경우 대부분의 벤치마크에서 성능 감소가 발생하여 기존 구조대비 평균 5.58% 감소율을 확인하였다. 반대로, 본 논문의 실험 환경에서의 L2 캐쉬의 적중률이 낮은 애플리케이션인 needle은 불필요한 L2 접근을 바이패스 함으로써 전체적인 성능 증가를 이끌어낸 것으로 분석된다.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.235-238
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• 2002

This paper proposes a novel scheme of designating non-cacheable addresses of memories in embedded systems of multi-master architectures without a Memory Management Unit (MMU). As a solution for data coherency problem between external memories and a cache memory, we proposes a cache masking scheme by allocating the most significant bit of address not used in 32-bit address system as indicator bit to designate non-cacheable address. As this scheme enables non-cacheable area designation every address, the simpler in the aspect of hardware and more flexible size of non-cacheable area can be obtained.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.1655-1658
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• 2004

Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture, called DAVID II, resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. The experimental results show that DAVID II achieves almost linear speedup at best case even in sixteen rasterizers.

• Journal of KIISE:Information Networking
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• v.30 no.5
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• pp.631-640
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• 2003

Because of multi-hop wireless communication, P2P applications in ad hoc networks suffer poor performance. We Propose neighbor caching strategy to overcome this shortcoming and show it is more efficient than self caching that nodes store data in theirs own cache individually. A node can extend its caching storage instantaneously with neighbor caching by borrowing the storage from idle neighbors, so overcome multi-hop wireless communications with data source long distance away from itself. We also present the ranking based prediction that selects the most appropriate neighbor which data can be stored in. The node that uses the ranking based prediction can select the neighbor that has high possibility to keep data for a long time and avoid caching the low ranked data. Therefore the ranking based prediction improves the throughput of neighbor caching. In the simulation results, we observe that neighbor caching has better performance, as large as network size, as long as idle time, and as small as cache size. We also show the ranking based prediction is an adaptive algorithm that adjusts times of data movement into the neighbor, so makes neighbor caching flexible according to the idleness of nodes

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.1
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• pp.155-163
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• 2014

To enhance network efficiency, content-centric networking (CCN) proposes that intermediated network nodes on a content-delivery path temporally cache transmitted contents. Then if an intermediated node receives a content request message (Interest) for previously cached content, the node directly transmits the cached content as a response message (Data) to requestors and finishes the transmission of the received Interest. Since Interest is performed by intermediated network nodes, it is possible to efficiently transmit contents and to effectively solve a network congestion problem caused around contents sources. For that, CCN utilizes both content store to temporarily cache content and pending Interest table (PIT) to record Interest incoming Face. However, it has mentioned the possibility of denial service attack using both the limitation of PIT resource and fake Interests. In this paper, we briefly describe the presented PIT flooding attack utilizing fake Interest. Then we introduce new attack possibility using fake Data and propose a countermeasure for the proposed attack. Also we evaluate the performance of our proposal.