• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.3
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• pp.27-33
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• 1999

We have investigated the ultra-low energy B, P, and As ion implantation using upgraded MDRANGE code to study formation of nanometer junction depths. Even at the ultra-low energies simulated in this paper, it was revealed that ion channeling should be carefully considered. It was estimated that ion channelings have much effect on dopant profiles when B ion implant energies were more than 500 eV, P more than 2 keV and As approximately more than 4 keV. When we compared 2-dimensional dopant profiles of 1 keV B with that of tilted one, 2 keV P with tilt, and 5 keV As with tilt, we could find that most channeling cases occurred not lateral directions but depth directions.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.8
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• pp.819-826
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• 2002

In this paper, the performance of Au / $Ba_{0.5}Sr_{0.5}TiO_3$ (BST) / Magnesium oxide (MgO) two-layered electrically tunable band-pass Filters (BPFs) is demonstrated. The devices consist of microstrip, coplanar waveguide (CPW), and conductor-backed coplanar waveguide (CBCPW) structures. These BST thin film band-pass filters have been designed by the 2.5 D field simulator, IE3D, Zeland Inc., and fabricated by thin film process. The simulation results, using the 2-pole microstrip, CPW, and CBCPW band-pass filters, show the center frequencies of 5.89 GHz, 5.88 GHz, and 5.69 GHz, and the corresponding insertion losses are 2.67 dB, 1.14 dB, and 1.60 dB, with 3 %, 9 %, and 7 % bandwidth, respectively. The measurement results show the center frequencies of 6.4 GHz, 6.14 GHz, and 6.04 GHz, and their corresponding insertion losses are 6 dB, 4.41 dB, and 5.41 dB, respectively, without any bias voltage. With the bias voltage of 40 V, the center frequencies for the band-pass filters are measured to be 6.61 GHz, 6.31 GHz, and 6.21 GHz, and their insertion losses are observed to be 7.33 dB, 5.83 dB, and 6.83 dB, respectively. From the experiment, the tuning range for the band-pass filters are determined as about 3 % ~ 8 %.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.259-262
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• 2006

This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications. The proposed circuit has been designed by using TSMC $0.18{\mu}m$ CMOS process and current-reused two-stage cascade topology. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results shows that the LNA has a extremely low power dissipation of 1.38mW with a $V_{DD}$ of 1.0V. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and noise figure of 1.13dB.

• Journal of Internet Computing and Services
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• v.8 no.1
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• pp.47-55
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• 2007

In this paper, we propose and observe a system that adopts Common-MCS (Modulation and Coding Scheme) level over all layer and Independent-MCS level for each layer in the combined AMC-V-BLAST (Adaptive Modulation and Coding-Vertical-Bell-lab Layered Space-Time) system. Also, comparing with the combined system using Common-MCS level, we observe throughput performance improvement in case of Independent-MCS level. As a result of simulation, Independent-MCS level case adapts modulation and coding scheme for maximum throughput to each channel condition in separate layer, resulting in improved throughput compared to Common-MCS level case. Especially, the results show that the combined AMC-V-BLAST system with Independent-MCS level achieves a gain of 700kbps in $7{\sim}9dB$ SNR (Signal-to-Noise Ratio) range against using Common-MCS level. In addition, the combined AMC-V-BLAST system using MMSEnulling method with receive diversity is verified that the difference of throughput between Independent MCS level system and common MCS level system in $7dB{\sim}9dB$ SNR is about 350kbps more or less.

• ETRI Journal
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• v.36 no.2
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• pp.321-324
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• 2014

This letter describes a two-phase clock oxide thin-film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART-SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from -4 V to 5 V at a line time of $5{\mu}s$. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively -12.6 dB and -26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16-stage shift registers at $V_{TH}=-1.56V$, compared to 11.5 mW for the conventional circuits.

• Journal of Korea Multimedia Society
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• v.5 no.6
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• pp.753-758
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• 2002

In this paper, low voltage 3V CMOS programmable gain amplifier(PGA) for using in the transmitter and receiver of ADSL analog front-end is designed. The designed receive PGA is connected with 1.1MHz continuous lowpass fillet and controls the gain from 0dB to 30dB. And also the transmitter PGA is connected with 138KHz lowpass filter and controls the gain from -15dB to 0dB. The gain of All PGAs can be programmed by digital logic circuits and main controller. The designed PGAs are verified using HSPICE simulation with $0.35\mu{m}$ CMOS parameter.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.109-114
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• 2023

In this paper, a 2-channel Image-Reject receiver using a 65-nm CMOS process is presented for Ka-band compact radars. The designed receiver consists of Low-Noise Amplifier (LNA), IQ mixer, and Analog Baseband (ABB). ABB includes a complex filter in order to suppress unwanted images, and the variable gain amplifiers (VGAs) in RF block and ABB have gain tuning range from 4.5-56 dB for wide dynamic range. The gain of the receiver is controlled by on-chip SPI controllers. The receiver has noise figure of <15 dB, OP1dB of >4 dBm, image rejection ratio of >30 dB, and channel isolation of >45 dB at the voltage gain of 36 dB, in the Ka-band target frequency. The receiver consumes 420 mA at 1.2 V supply with die area of 4000×1600 ㎛.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.14-21
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• 2011

A 10b 500MS/s $0.13{\mu}m$ CMOS ADC is proposed for 4G wireless communication systems such as a LTE-Advanced and SDR The ADC employs a calibration-free single-channel folding architecture for low power consumption and high speed conversion rate. In order to overcome the disadvantage of high folding rate, at the fine 7b ADC, a cascaded folding-interpolating technique is proposed. Further, a folding amplifier with the folded cascode output stage is also discussed in the block of folding bus, to improve the bandwidth limitation and voltage gain by parasitic capacitances. The chip has been fabricated with $0.13{\mu}m$ 1P6M CMOS technology, the effective chip area is $1.5mm^2$. The measured results of INL and DNL are within 2.95LSB and l.24LSB at 10b resolution, respectively. The SNDR is 54.8dB and SFDR is 63.4dBc when the input frequency is 9.27MHz at sampling frequency of 500MHz. The ADC consumes 150mW($300{\mu}W/MS/s$) including peripheral circuits at 500MS/s and 1.2V(1.5V) power supply.

• Journal of Broadcast Engineering
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• v.14 no.1
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• pp.70-80
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• 2009

We propose an ideal line coding for high speed data communication in visible light communication system. B4-HBT line coding is defined as follow. The 1 bit is +V at first though 1 encodes +Voltage and -Voltage doing change of shift each other, then -V newly. V that is been mutually contradictory for 1 bit that exist before that if continuous 0 bits exist 4 here same and reduces mistake because has reverse mark V in 4 continuous last 0 bits and gives half bit variation in 1 bit and made effect of noise low. 2${\sim}$3 dB profit is seen comparing with line coding that exist in simulation result.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.492-498
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• 2003

In this paper, We analyze the optimum bias conditions of cascode coupled microwave mixer for maximum conversion gain mixer. Microwave self-oscillating mixer by two GaAs MESFET cascode coupled, to upper GaAs MESFET operating as a oscillator with high Q dielectric resonator and the lower GaAs MESFET operated as a mixer with low noise and high conversion characteristics. As a result of experiments, cascode coupled microwave self oscillating mixer according to optimun bias shows an 5.92 dBm oscillating power, -132.0dBc/Hz @ 100KHz at 5.15GHz and 3dB conversion loss.