• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.637-638
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• 2006

A novel 1.2V class-AB output stage for the SW-OpAmp technique was presented. By using current mirrors and simple current extraction circuits, the proposed circuit boosts DM signal currents while eliminates CM ones to perform class-AB operation. Hspice simulation results verify the versatility of the proposed circuit technique.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.108-110
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• 2018

This paper proposes shortcircuit fault protection method in a synchronous buck converter using the PCB pattern Rogowski coil. The PCB pattern Rogowski coils are embedded in the gate driver to measure the device currents of the top and bottom side. When shortcircuit occurs in the system, the gate signal is blocked by the proposed fault protection method using the device current. The simulation and experimental results show that the proposed fault protection method is verified in the shortcircuit system.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.3
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• pp.374-382
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• 2018

This paper has done a hardware-based approach to increase the modulation index in 3-phase inverters, unlike the conventional software algorithm-based approaches. The minimum required time to measure the currents in a three-phase inverters with shunt resistors has also been analyzed. By the analysis, the longest time in minimum required time is AD conversion time. To shorten the minimum required time, this paper proposed a sample-and-hold(S/H) circuit implemented at the inverter current signal output to retain the current signal. When the linear operation region of an inverter with S/H was compared with that without it, the modulation index was increased by 7.8 %. Inverters with S/H circuits can employ the traditional software algorithms, such as the voltage injection method or current restoration method, and it will yield further increase the modulation index.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.300-302
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• 2002

In this paper the high-speed fault current detector for superconducting fault current limiter is described. Detecting and interrupting the fault currents as quickly as possible is required in order not to exceed the thermal capacity of superconducting fault current limiter. A detecting method of an instantaneous fault current magnitude is adopted in the equipment described in this paper and a current signal through an analog/digital(A/D) converter would be compared with the reference in the digital signal processor(DSP). Around 20ms has elapsed for detecting the fault current. It is necessary to establish the appropriate trade-off between the reliability and detection speed.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.31-33
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• 2007

This work presents the simplified mechanism that the microstrip line generates the radiated emission which is one of the measures on the EMI levels. The electric currents on the metallization of the structure are input to the radiation integrals with the Green's functions being derived to consider the stratification of the microstrip. The simulated results suggest the method of the conceptualization on the RE characteristics of the signal trace in the PCB structure.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.3
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• pp.362-368
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• 2009

Electrical fires have been occurred continuously in spite of installing ELB. Therefore the concern with the electrical arc-fault that cause the fire has growing. This paper measured series arc fault currents by the method of arc generator test in UL standard 1699. The used analysis methods in this paper are three different ways using DWT(discrete wavelet transform) those are frequently used for the arc fault current signal analysis. The arc fault detection probability is 100 % by method using noise-energy/shoulder-duration ratio of approximation coefficient. As these results, the variation of noise-energy and shoulder-duration ratio of approximation coefficient are founded important factors for the analysis of arc fault.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.156-161
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• 1996

Accurate equivalent circuit modeling using multi-circuit optimization has been perfomred for detemining small-signal model of AlGaAs/GaAs HBTs. Three equivalent circuits for a cutoff biasing and two active biasing at different curretns are optimized simultaneously to fit gheir S parameters under the physics-based constrain that current-dependent elements for one of active circuits are connected to those for another circit multiplied by the ratio of two currents. The cutoff mode circuit and the physical constrain give the advantage of extracting physically acceptable parameters, because the number of unknown variables. After this optimization, three ses of optimized model S-parameters agree well with their measured S-parameters from 0.045 GHz to 26.5GHz.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.199-204
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• 2007

This paper presents design of interleave configured dc-dc converter for high power distributed power system applications. The multi channel interleaving buck converter with small inductance has proved to be suitable for micro-grid, requiring medium output voltages, high output currents and fast transient response. Integrated magnetic components are used to reduce the size of the converter and improve efficiency. Unlike conventional methods, the distributed approach requires no centralized control, automatically accommodates varying numbers of converter cells, and is highly tolerant of subsystem failures. A general methodology for achieving distributed interleaving is proposed, along with a specific implementation approach. The design and simulation verification of switching frequency 10 kHz system is presented with interleaved clocking of the converter cells. The simulation (simulated by PSIM 6.1) results corroborate the analytical predictions and demonstrate the tremendous benefits of the distributed interleaving approach.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.6
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• pp.910-916
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• 1999

This paper presents the effective improvement of the thermal runaway phenomenon in high power SSPA when the RF input signal is not provided. The total gate resistors are optimized by the experiments and deducing the variation of velocity and currents of thermal runaway, which is based on manufacturer's recommendation. Especially, it is solved the complex thermal runaway that related gate resistors with the gate voltage variable circuit. The result of this paper is able to apply for improving the thermal runaway in existence of high power SSPA for WLL, cellular system and PCS repeater.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.10 s.241
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• pp.1336-1343
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• 2005

The detection mechanism of the flaw for the nondestructive testing using eddy current is related to the interaction of the induced eddy currents in the test specimen with flaws and the coupling of these interaction effects with the moving test probe. In this study, the two-dimensional electromagnetic finite element analysis(FEM) fur the eddy current signals of the aluminum plate with different depth of surface cracks is described and the comparison is also made between experimental and predicted signals analyzed by FEM. In addition, the characteristics of attenuation of the eddy current density due to the variation of the depth of a conductor are evaluated. The effective parameters for the application of eddy current technique to evaluate surface cracks are discussed by analyzing the characteristics of the eddy current signals due to the variation of crack depths.